NCP1203
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7
APPLICATION INFORMATION
Introduction
The NCP1203 implements a standard current mode
architecture where the switchoff time is dictated by the
peak current setpoint. This component represents the ideal
candidate where low partcount is the key parameter,
particularly in lowcost ACDC adapters, auxiliary
supplies etc. Due to its highperformance SMARTMOS
HighVoltage technology, the NCP1203 incorporates all the
necessary components normally needed in UC384X based
supplies: timing components, feedback devices, lowpass
filter and startup device. This later point emphasizes the fact
that ON Semiconductors NCP1203 does not need an
external startup resistance but supplies the startup current
directly from the highvoltage rail. On the other hand, more
and more applications are requiring low noload standby
power, e.g. for ACDC adapters, VCRs etc. UC384X series
have a lot of difficulty to reduce the switching losses at low
power levels. NCP1203 elegantly solves this problem by
skipping unwanted switching cycles at a useradjustable
power level. By ensuring that skip cycles take place at low
peak current, the device ensures quiet, noise free operation.
Finally, an autorecovery output shortcircuit protection
(OCP) prevents from any lethal thermal runaway in
overload conditions.
Startup Sequence
When the power supply is first powered from the mains
outlet, the internal current source (typically 6.0 mA) is
biased and charges up the V
CC
capacitor. When the voltage
on this V
CC
capacitor reaches the V
CC(on)
level (typically
12.8 V), the current source turns off and no longer wastes
any power. At this time, the V
CC
capacitor only supplies the
controller and the auxiliary supply is supposed to take over
before V
CC
collapses below V
CC(min)
. Figure 13 shows the
internal arrangement of this structure:
Figure 13. The Current Source Brings V
CC
Above 12.8 V and then Turns Off
-
+
8
6
4
6 mA or 0
CV
CC
Aux
HV
12.8 V/4.9 V
Once the power supply has started, the V
CC
shall be
constrained below 16 V, which is the maximum rating on
pin 6. Figure 14 portrays a typical startup sequence with a
V
CC
regulated at 12.5 V:
Figure 14. A Typical Startup Sequence for
the NCP1203
t, TIME (sec)
3.00 M 8.00 M 13.0 M 18.0 M 23.0 M
13.5
12.5
11.5
10.5
9.5
REGULATION
12.8 V
NCP1203
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CurrentMode Operation
As the UC384X series, the NCP1203 features a
wellknown current mode control architecture which
provides superior input audiosusceptibility compared to
traditional voltagemode controllers. Primary current
pulsebypulse checking together with a fast over current
comparator offers greater security in the event of a difficult
fault condition, e.g. a saturating transformer.
Adjustable Skip Cycle Level
By offering the ability to tailor the level at which the skip
cycle takes place, the designer can make sure that the skip
operation only occurs at low peak current. This point
guarantees a noisefree operation with cheap transformers.
Skip cycle offers a proven mean to reduce the standby power
in no or light loads situations.
Wide SwitchingFrequency Offer
Four different options are available: 40 kHz 65 kHz –
100 kHz. Depending on the application, the designer can
pick up the right device to help reducing magnetics or
improve the EMI signature before reaching the 150 kHz
starting point.
Overcurrent Protection (OCP)
When the auxiliary winding collapses below UVLOlow,
the controller stops switching and reduces its consumption.
It stays in this mode until Vcc reaches 4.9 V typical, where
the startup source is reactivated and a new startup sequence
is attempted. The power supply is thus operated in burst
mode and avoids any lethal thermal runaway. When the
default goes way, the power supply automatically resumes
operation.
Wide DutyCycle Operation
Wide mains operation requires a large dutycycle
excursion. The NCP1203 can go up to 80% typically.
Low Standby Power
If SMPS naturally exhibit a good efficiency at nominal
load, they begin to be less efficient when the output power
demand diminishes. By skipping unneeded switching
cycles, the NCP1203 drastically reduces the power wasted
during light load conditions. In noload conditions, the
NCP1203 allows the total standby power to easily reach next
International Energy Agency (IEA) recommendations.
No Acoustic Noise while Operating
Instead of skipping cycles at high peak currents, the
NCP1203 waits until the peak current demand falls below a
useradjustable 1/3
rd
of the maximum limit. As a result,
cycle skipping can take place without having a singing
transformer You can thus select cheap magnetic
components free of noise problems.
External MOSFET Connection
By leaving the external MOSFET external to the IC, you
can select avalanche proof devices which, in certain cases
(e.g. low output powers), let you work without an active
clamping network. Also, by controlling the MOSFET gate
signal flow, you have an option to slow down the device
commutation, therefore reducing the amount of
ElectroMagnetic Interference (EMI).
SPICE Model
A dedicated model to run transient cyclebycycle
simulations is available but also an averaged version to help
you closing the loop. Readytouse templates can be
downloaded in OrCAD’s Pspice and INTUSOFT’s from ON
Semiconductor web site, NCP1203 related section.
Overload Operation
In applications where the output current is purposely not
controlled (e.g. wall adapters delivering raw DC level), it is
interesting to implement a true shortcircuit protection. A
shortcircuit actually forces the output voltage to be at a low
level, preventing a bias current to circulate in the
optocoupler LED. As a result, the auxiliary voltage also
decreases because it also operates in Flyback and thus
duplicates the output voltage, providing the leakage
inductance between windings is kept low. To account for this
situation and properly protect the power supply, NCP1203
hosts a dedicated overload detection circuitry. Once
activated, this circuitry imposes to deliver pulses in a burst
manner with a low dutycycle. The system autorecovers
when the fault condition disappears.
During the startup phase, the peak current is pushed to the
maximum until the output voltage reaches its target and the
feedback loop takes over. The auxiliary voltage takes place
after a few switching cycles and selfsupplies the IC. In
presence of a short circuit on the output, the auxiliary
voltage will go down until it crosses the undervoltage
lockout level of typically 7.8 V. When this happens,
NCP1203 immediately stops the switching pulses and
unbias all unnecessary logical blocks. The overall
consumption drops, while keeping the gate grounded, and
the V
CC
slowly falls down. As soon as V
CC
reaches typically
4.8 V, the startup source turnson again and a new startup
sequence occurs, bringing V
CC
toward 12.8 V as an attempt
to restart. If the default has gone, then the power supply
normally restarts. If not, a new protective burst is initiated,
shielding the SMPS from any runaway. Figure 15, on the
following page, portrays the typical operating signals in
short circuit.
NCP1203
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Figure 15. Typical Waveforms in Short Circuit Conditions
7.8 V
12.8 V
4.9 V
V
CC
DRIVING
PULSES
Calculating the V
CC
Capacitor
The V
CC
capacitor can be calculated knowing the IC
consumption as soon as V
CC
reaches 12.8 V. Suppose that a
NCP1203P60 is used and drives a MOSFET with a 30 nC
total gate charge (Qg). The total average current is thus made
of ICC1 (700 mA) plus the driver current, Fsw x Qg or
1.8 mA. The total current is therefore 2.5 mA. The DV
available to fully startup the circuit (e.g. never reach the
7.8 V UVLO during power on) is 12.8–7.8 = 5 V. We have
a capacitor who then needs to supply the NCP1203 with
2.5 mA during a given time until the auxiliary supply takes
over. Suppose that this time was measured at around 15 ms.
CV
CC
is calculated using the equation
C +
Dt·i
DV
or
C w 7.5 mF
. Select a 22 mF/16 V and this will fit.
Skipping Cycle Mode
The NCP1203 automatically skips switching cycles when
the output power demand drops below a given level. This is
accomplished by monitoring the FB pin. In normal
operation, pin 2 imposes a peak current accordingly to the
load value. If the load demand decreases, the internal loop
asks for less peak current. When this setpoint reaches a
determined level (Vpin 1), the IC prevents the current from
decreasing further down and starts to blank the output
pulses: the IC enters the socalled skip cycle mode, also
named controlled burst operation. The power transfer now
depends upon the width of the pulse bunches (Figure 17).
Suppose we have the following component values:
Lp, primary inductance = 350 mH
Fsw , switching frequency = 61 kHz
Ip skip = 600 mA (or 333 mV/Rsense)
The theoretical power transfer is therefore:
1
2
·Lp·Ip
2
·Fsw+ 3.8 W
If this IC enters skip cycle mode with a bunch length of
10 ms over a recurrent period of 100 ms, then the total power
transfer is:
3.8 . 0.1 + 380 mW
.
To better understand how this skip cycle mode takes place,
a look at the operation mode versus the FB level
immediately gives the necessary insight:
Figure 16.
SKIP CYCLE OPERATION
I
P(min)
= 333 mV/R
SENSE
NORMAL CURRENT
MODE OPERATION
FB
1 V
4.2 V, FB Pin Open
3.2 V, Upper
Dynamic Range
When FB is above the skip cycle threshold (1.0 V by
default), the peak current cannot exceed 1.0 V/Rsense.
When the IC enters the skip cycle mode, the peak current
cannot go below Vpin1/3.3/Rsense. The user still has the
flexibility to alter this 1.0 V by either shunting pin 1 to
ground through a resistor or raising it through a resistor up
to the desired level. Grounding pin 1 permanently
invalidates the skip cycle operation. However, given the
extremely low standby power the controller can reach, the
PWM in noload conditions can quickly enter the minimum
t
on
and still transfer too much power. An instability can take
place. We recommend in that case to leave a little bit of skip
level to always allow 0% duty cycle.

NCP1203D60R2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Switching Controllers 60KHz Current Mode SMPS PWM
Lifecycle:
New from this manufacturer.
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