MAX1002
The MAX1002 features a proprietary encoding scheme
that ensures no more than 1LSB dynamic encoding
error. Dynamic encoding errors resulting from meta-
stable states may occur when the analog input voltage,
at the time the sample is taken, falls close to the deci-
sion point for any one of the input comparators. The
resulting output code for typical converters can be
incorrect, including false full- or zero-scale outputs. The
MAX1002’s unique design reduces the magnitude of
this type of error to 1LSB.
Internal Voltage Reference
An internal buffered bandgap reference is included on
the MAX1002 to drive the ADC’s reference ladders. The
on-chip reference and buffer eliminate any external
(high-impedance) connections to the reference ladder,
minimizing the potential for noise coupling from exter-
nal circuitry while ensuring that the voltage reference,
input amplifier, and reference ladder track well with
variations in temperature and power supplies.
Oscillator Circuit
The MAX1002 includes a differential oscillator, which is
controlled by an external parallel resonant (tank) net-
work (Figure 6). As an alternative, the oscillator may be
overdriven with an external clock source (Figure 7).
Internal-Clock Operation (Tank)
If the tank circuit is used, the resonant inductor should
have a sufficiently high Q and a self-resonant frequen-
cy (SRF) of at least twice the intended oscillator fre-
quency. Coilcraft's 1008HS-221, with a 700MHz SRF
and a Q of 45, works well for this application. Generate
different clock-frequency ranges by adjusting varactor
and tank elements.
An internal-clock-driver buffer is included to provide
sharp clock edges to the internal flash comparators.
The buffer ensures that the comparators are simultane-
ously clocked, maximizing the ADC’s effective number
of bits of performance.
External-Clock Operation
To accommodate designs that use an external clock,
the MAX1002’s internal oscillator can be overdriven by
an external clock source (Figure 7). The external clock
source should be a sinusoid to minimize clock-phase
noise and jitter, which can degrade the ADC’s effective
bits performance. AC couple the clock source (recom-
mended voltage level is approximately 1Vp-p) to the
oscillator inputs (Figure 7).
Low-Power, 60Msps, Dual, 6-Bit ADC
8 _______________________________________________________________________________________
Figure 6. Tank-Resonator Oscillator
Figure 7. External-Clock-Drive Circuit
