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MAX1002CAX+T

P1-P3P4-P6P7-P9P10-P12
_______________General Description
The MAX1002 is a dual, 6-bit analog-to-digital converter
(ADC) that combines high-speed, low-power operation
with a user-selectable input range, an internal refer-
ence, and a clock oscillator. The dual, parallel ADCs
are designed to convert in-phase (I) and quadrature
(Q) analog signals into two 6-bit offset-binary-coded
digital outputs at sampling rates up to 60Msps while
achieving typical integral nonlinearity (INL) and differ-
ential nonlinearity (DNL) of ±1/4LSB. The ability to
interface directly with baseband I and Q signals makes
the MAX1002 ideal for use in direct-broadcast satellite,
VSAT, and QAM16 demodulation applications.
The MAX1002 input amplifiers feature true differential
inputs, a 55MHz -0.5dB analog bandwidth, and user-
programmable input full-scale ranges of 125mVp-p,
250mVp-p, or 500mVp-p. With an AC-coupled input
signal, matching performance between input channels
is typically 0.1dB gain, 1/4LSB offset, and 0.5° phase.
Dynamic performance is 5.85 effective number of bits
(ENOB) with a 20MHz analog input signal, or 5.78
ENOB with a 50MHz input signal.
The MAX1002 operates with a single +5V power supply
and provides TTL-compatible digital outputs. The device
is available in the commercial temperature range (0°C to
+70°C) and comes in a 36-pin SSOP package.
________________________Applications
Direct Broadcast Satellite (DBS) Receivers
VSAT Receivers
Wide Local Area Networks (WLAN)
Cable Television Set-Top Boxes
____________________________Features
♦ ±1/4LSB INL and DNL, Typical
♦ 1/4LSB (typ) Channel-to-Channel Offset Matching
♦ 0.1dB Gain and 0.5° Phase Matching, Typical
♦ Internal Bandgap Voltage Reference
♦ Two Matched 6-Bit, 60Msps ADCs
♦ Excellent Dynamic Performance:
5.85 ENOB with 20MHz Analog Input
5.7 ENOB with 50MHz Analog Input
♦ Internal Oscillator with Overdrive Capability
♦ 55MHz (-0.5dB) Bandwidth Input Amplifiers
with True Differential Inputs
♦ User-Selectable Input Full-Scale Range
(125mVp-p, 250mVp-p, or 500mVp-p)
♦ Single-Ended or Differential Input Drive
♦ +5V Single Supply
♦ TTL Outputs
♦ 90Msps Upgrade with +3.3V CMOS-Compatible
Output Available (MAX1003)
MAX1002
Low-Power, 60Msps, Dual, 6-Bit ADC
________________________________________________________________
Maxim Integrated Products
1
MAX1002
DATA
BUFFER
Q
CLOCK
DRIVER
D0I–D5I
DCLK
TNK+
TNK-
DQ0–DQ5
INPUT
AMP
I
IIN+
IIN-
GAIN
QIN+
QIN-
CLOCK
OUT
DATA
BUFFER
I
6
ADC
I
ADC
Q
VREF
VREF
BANDGAP
REFERENCE
OFFSET
CORREC-
TION Q
OFFSET
CORREC-
TION I
INPUT
AMP
Q
QOCC+ QOCC-
IOCC+ IOCC-
6
6
6
_________________________________________________________Functional Diagram
19-1270; Rev 0; 7/97
PART
MAX1002CAX 0°C to +70°C
TEMP. RANGE PIN-PACKAGE
36 SSOP
EVALUATION KIT
AVAILABLE
______________Ordering Information
Pin Configuration appears at end of data sheet.
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800
For small orders, phone 408-737-7600 ext. 3468.
MAX1002
Low-Power, 60Msps, Dual, 6-Bit ADC
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS
(V
CC
, V
CCO
= +5V ±5%; T
A
= T
MIN
to T
MAX
; unless otherwise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
V
CC
to GND .........................................................-0.3V to +6.5V
V
CCO
to OGND.........................................................-0.3V, +6.5V
GND to OGND .........................................................-0.3V, +0.3V
Digital and Clock Output Pins to OGND ........-0.3V, V
CCO
(<10sec)
All Other Pins to GND..................................................-0.3V, V
CC
Continuous Power Dissipation (T
A
= +70°C)
SSOP (derate 45mW/°C above +70°C) ......................941mW
Operating Temperature Range...............................0°C to +70°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, <10sec)...........................+300°C
CONDITIONS
LSB-0.5 ±0.25 0.5INLIntegral Nonlinearity
Bits6RESResolution
UNITSMIN TYP MAXSYMBOLPARAMETER
GAIN = open (mid gain)
GAIN = V
CC
(high gain)
No missing codes over temperature
237.5 250 262.5V
FSM
118.75 125 131.25V
FSH
LSB-0.5 ±0.25 0.5DNLDifferential Nonlinearity
Other analog input driven with external source
(Note 2)
Guaranteed by design
V1.75 2.75V
CM
GAIN = GND (low gain)
Common-Mode Voltage Range
pF3 5C
IN
Input Capacitance
kΩ13 20 29R
IN
Input Resistance
V2.25 2.35 2.45V
AOC
Input Open-Circuit Voltage
mVp-p
475 500 525V
FSL
Full-Scale Input Range
Other oscillator input tied to V
CC
+ 0.3V
I
SOURCE
= 50µA V2.4V
OH
Digital Outputs Logic-High
Voltage
kΩ4.8 8 12.1R
OSC
Oscillator Input Resistance
I
SINK
= 400µA V0.5V
OL
Digital Outputs Logic-Low
Voltage
V
CC
= 4.75V to 5.25V (Note 3)
20MHz, FS I & Q analog inputs,
C
LOAD
= 15pF (Note 4)
mW380PDPower Dissipation
mA24I
CCO
Digital Outputs Supply Current
dB-75 -40PSRRPower-Supply Rejection Ratio
mA63 104I
CC
Supply Current
DC ACCURACY (Note 1)
INVERTING AND NONINVERTING ANALOG INPUTS
OSCILLATOR INPUTS
DIGITAL OUTPUTS (DI0–DI5, DQ0–DQ5)
POWER SUPPLY
MAX1002
Low-Power, 60Msps, Dual, 6-Bit ADC
_______________________________________________________________________________________ 3
AC ELECTRICAL CHARACTERISTICS
(V
CC,
V
CCO
= +5V ±5%; T
A
= +25°C; unless otherwise noted.)
Note 1: Best straight-line linearity method.
Note 2: A typical application will AC couple the analog input to the DC bias level present at the analog inputs (typically 2.35V).
However, it is also possible to DC couple the analog input (using differential or single-ended drive) within this common-
mode input range (Figures 4, 5).
Note 3: PSSR is defined as the change in the mid-gain, full-scale range as a function of the variation in V
CC
supply voltage
(expressed in decibels).
Note 4: The current in the V
CCO
supply is a strong function of the capacitive loading on the digital outputs. To minimize supply
transients and achieve the best dynamic performance, reduce the capacitive loading effects by keeping line lengths on the
digital outputs to a minimum.
Note 5: Offset-correction compensation enabled, 0.22µF at Q and I compensation inputs (Figures 2, 3).
Note 6: t
PD
and t
SKEW
are measured from the 1.4V level of the output clock, to the 1.4V level of either the rising or falling edge of a
data bit. t
DCLK
is measured from the 50% level of the clock overdrive signal on TNK+ to the 1.4V level of D
CLK
. The capac-
itive load on the outputs is 15pF.
Gain = GND, open, V
CC
GAIN = open (mid gain),
V
IN
= 50MHz, -1dB below FS
GAIN = open (mid gain)
5.7
ENOB
M
5.6 5.85
Effective Number of Bits
Gain = open (mid gain)
Gain = V
CC
(low gain)
Q channel
I channel
dB
CONDITIONS
MHz55BWAnalog Input -0.5dB Bandwidth
Msps60f
MAX
Maximum Sample Rate
-55XTLK
Gain = V
CC
(high gain)
Crosstalk Between ADCs
LSB
-0.5 0.5
OFFInput Offset (Note 5)
-0.5 0.5
dB35.4 37SINAD
Signal-to-Noise and Distortion
Ratio
Bits
5.85ENOB
L
5.8ENOB
H
(Note 5)
dB-0.2 ±0.1 0.2AM
Amplitude Match Between
ADCs
LSB-0.5 ±0.25 0.5OMM2Offset Mismatch Between ADCs
(Note 6)
(Note 6)
ns3.6t
SKEW
Data Valid Skew
ns7.1t
PD
DCLK to Data-Propagation
Delay
degrees-2 ±0.5 2PM
UNITSMIN TYP MAXSYMBOLPARAMETER
Phase Match Between ADCs
TNK+ to DCLK (Note 6) ns5.3t
DCLK
Input to DCLK Delay
ns5.5t
AP
Aperture Delay
clock
cycle
1PDPipeline Delay
DYNAMIC PERFORMANCE (GAIN = open; external 60MHz clock (Figure 7); V
INI
, V
INIQ
= 20MHz sine; amplitude -1dB below FS;
unless otherwise noted.)
TIMING CHARACTERISTICS (data outputs: R
L
= 1MΩ, C
L
= 15pF, Figure 8)
P1-P3P4-P6P7-P9P10-P12

MAX1002CAX+T

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Buy MAX1002CAX+T
Manufacturer:
Maxim Integrated
Description:
Analog to Digital Converters - ADC Low-Power 60Msps Dual 6-Bit
Lifecycle:
New from this manufacturer.
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