8©2015 Integrated Device Technology, Inc December 7, 2015
87972I-147 Datasheet
Table 5. Input Frequency Characteristics, V
DD
= V
DDA
= V
DDO
= 3.3V ± 5%, T
A
= -40°C to 85°C
NOTE 1: Input frequency depends on the feedback divide ratio to ensure "clock * feedback divide" is in the VCO range of 240MHz to
500MHz.
Table 6. Crystal Characteristics
AC Electrical Characteristics
Table 7. AC Characteristics, V
DD
= V
DDA
= V
DDO
= 3.3V ± 5%, T
A
= -40°C to 85°C
NOTE 1: Defined as the time difference between the input reference clock and the average feedback input signal when the PLL is locked
and the input reference frequency is stable.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
DDO
/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
F
IN
Input Frequency
CLK0, CLK1; NOTE 1 150 MHz
XTAL1, XTAL 12 40 MHz
FRZ_CLK 20 MHz
Parameter Test Conditions Minimum Typical Maximum Units
Mode of Oscillation Fundamental
Frequency 12 40 MHz
Equivalent Series Resistance (ESR) 50
Shunt Capacitance 7pF
Parameter Symbol Test Conditions Minimum Typical Maximum Units
f
MAX
Output Frequency
÷2 150 MHz
÷4 125 MHz
÷6 83.33 MHz
÷8 62.5 MHz
t(Ø)
Static Phase
Offset; NOTE 1
CLK0
QFB ÷ 8,
In Frequency = 50MHz
-10 145 300 ps
CLK1 -65 90 245 ps
tsk(o) Output Skew; NOTE 2, 3 200 ps
tjit(cc) Cycle-to-Cycle Jitter; NOTE 3 All Banks ÷ 4 55 ps
f
VCO
PLL VCO Lock Range 240 500 MHz
t
LOCK
PLL Lock Time; NOTE 4 10 ms
t
R
/ t
F
Output Rise/Fall Time 0.8V to 2V 0.15 0.7 ns
odc Output Duty Cycle 45 55 %
t
PZL,
t
PZH
Output Enable Time; NOTE 4 10 ns
t
PLZL,
t
PHZ
Output Disable Time; NOTE 4 8 ns
