4©2015 Integrated Device Technology, Inc December 7, 2015
87972I-147 Datasheet
Table 1. Pin Descriptions
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Number Name Type Description
1 GNDI Power Power supply ground.
2 nMR/OE Input Pullup
Master reset and output enable. When HIGH, enables the outputs.
When LOW, resets the outputs to Hi-Z and resets output divide circuitry.
Enables and disables all outputs. LVCMOS / LVTTL interface levels.
3 FRZ_CLK Input Pullup Clock input for freeze circuitry. LVCMOS / LVTTL interface levels.
4 FRZ_DATA Input Pullup Configuration data input for freeze circuitry. LVCMOS / LVTTL interface levels.
5,
26,
27
FSEL_FB2,
FSEL_FB1,
FSEL_FB0
Input Pullup
Select pins control Feedback Divide value. LVCMOS / LVTTL interface levels.
See Table 3B.
6 PLL_SEL Input Pullup
Selects between the PLL and reference clocks as the input to the output dividers.
When HIGH, selects PLL. When LOW, bypasses the PLL and reference clocks.
LVCMOS / LVTTL interface levels.
7 REF_SEL Input Pullup
Selects between crystal and reference clock. When LOW, selects CLK0 or CLK1.
When HIGH, selects crystal inputs. LVCMOS / LVTTL interface levels.
8 CLK_SEL Input Pullup
Clock select input. When LOW, selects CLK0. When HIGH, selects CLK1.
LVCMOS / LVTTL interface levels.
9, 10 CLK0, CLK1 Input Pullup Single-ended reference clock inputs. LVCMOS/LVTTL interface levels.
11,
12
XTAL_1,
XTAL_2
Input Crystal oscillator interface. XTAL_1 is the input. XTAL_2 is the output.
13 V
DDA
Power Analog supply pin.
14 INV_CLK Input Pullup Inverted clock select for QC2 and QC3 outputs. LVCMOS / LVTTL interface levels.
15, 24, 30,
35, 39, 47,
51
GNDO Power Power supply ground.
16, 18,
21, 23
QC3, QC2,
QC1, QC0
Output Single-ended Bank C clock outputs. LVCMOS/ LVTTL interface levels.
17, 22, 33,
37, 45, 49
V
DDO
Power Output power supply pins.
19,
20
FSEL_C1,
FSEL_C0
Input Pullup Select pins for Bank C outputs. LVCMOS / LVTTL interface levels. See Table 3A.
25 QYSNC Output
Synchronization output for Bank A and Bank C. Refer to Figure 1, Timing Diagrams.
LVCMOS / LVTTL interface levels.
28 V
DD
Power Power supply pin.
29 QFB Output Single-ended feedback clock output. LVCMOS / LVTTL interface levels.
31 EXT_FB Input Pullup External feedback. LVCMOS / LVTTL interface levels.
32, 34,
36, 38
QB3, QB2,
QB1, QB0
Output Single-ended Bank B clock outputs. LVCMOS/ LVTTL interface levels.
40,
41
FSEL_B1,
FSEL_B0
Input Pullup Select pins for Bank B outputs. LVCMOS / LVTTL interface levels. See Table 3A.
42,
43
FSEL_A1,
FSEL_A0
Input Pullup Select pins for Bank A outputs. LVCMOS / LVTTL interface levels. See Table 3A.
44, 46
48, 50
QA3, QA2,
QA1, QA0
Output Single-ended Bank A clock outputs. LVCMOS/ LVTTL interface levels.
52 VCO_SEL Input Pullup
Selects VCO. When HIGH, selects VCO ÷ 1. When LOW, selects VCO ÷ 2.
LVCMOS / LVTTL interface levels.
