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MC74HCT573ADWR2G

P1-P3P4-P6
© Semiconductor Components Industries, LLC, 2014
September, 2014 − Rev. 13
1 Publication Order Number:
MC74HCT573A/D
MC74HCT573A
Octal 3-State Noninverting
Transparent Latch with
LSTTL Compatible Inputs
High−Performance Silicon−Gate CMOS
The MC74HCT573A is identical in pinout to the LS573. This
device may be used as a level converter for interfacing TTL or NMOS
outputs to High−Speed CMOS inputs.
These latches appear transparent to data (i.e., the outputs change
asynchronously) when Latch Enable is high. When Latch Enable goes
low, data meeting the setup and hold times becomes latched.
The Output Enable input does not affect the state of the latches, but
when Output Enable is high, all device outputs are forced to the
high−impedance state. Thus, data may be latched even when the
outputs are not enabled.
The HCT573A is identical in function to the HCT373A but has the
Data Inputs on the opposite side of the package from the outputs to
facilitate PC board layout.
Features
• Output Drive Capability: 15 LSTTL Loads
• TTL/NMOS−Compatible Input Levels
• Outputs Directly Interface to CMOS, NMOS and TTL
• Operating Voltage Range: 4.5 to 5.5 V
• Low Input Current: 10 mA
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7 A
• Chip Complexity: 234 FETs or 58.5 Equivalent Gates
♦ Improved Propagation Delays
♦ 50% Lower Quiescent Power
• These Devices are Pb−Free and are RoHS Compliant
LOGIC DIAGRAM
DATA
INPUTS
D0
D1
D2
D3
D4
D5
D6
D7
LATCH ENABLE
OUTPUT ENABLE
11
1
9
8
7
6
5
4
3
219
18
17
16
15
14
13
12
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
PIN 20 = V
CC
PIN 10 = GND
NONINVERTING
OUTPUTS
http://onsemi.com
Device Package Shipping
†
ORDERING INFORMATION
MC74HCT573ADWR2G SOIC−20
(Pb−Free)
1000 /
Tape & Ree
l
MC74HCT573ADTR2G TSSOP−20
(Pb−Free)
2500 /
Tape & Ree
l
1
20
MARKING DIAGRAMS
SOIC−20
HCT573A
AWLYYWWG
HCT
573A
ALYWG
G
TSSOP−20
20
1
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
SOIC−20
DW SUFFIX
CASE 751D
TSSOP−20
DT SUFFIX
CASE 948E
PIN ASSIGNMENT
D4
D2
D1
D0
OUTPUT
ENABLE
GND
D7
D6
D5
D3
5
4
3
2
1
10
9
8
7
6
14
15
16
17
18
19
20
11
12
13
Q3
Q2
Q1
Q0
V
CC
LATCH
ENABLE
Q7
Q6
Q5
Q4
MC74HCT573A
http://onsemi.com
2
FUNCTION TABLE
Inputs Output
Output Latch
Enable Enable D Q
LHHH
LHLL
L L X No Change
HXXZ
X = Don’t Care
Z = High Impedance
Design Criteria
Value Units
Internal Gate Count* 58.5 ea
Internal Gate Propagation Delay 1.5 ns
Internal Gate Power Dissipation 5.0
mW
Speed Power Product 0.0075 pJ
*Equivalent to a two−input NAND gate.
MAXIMUM RATINGS
Symbol Parameter Value Unit
V
CC
DC Supply Voltage (Referenced to GND) –0.5 to + 7.0 V
V
in
DC Input Voltage (Referenced to GND) –0.5 to V
CC
+ 0.5 V
V
out
DC Output Voltage (Referenced to GND) –0.5 to V
CC
+ 0.5 V
I
in
DC Input Current, per Pin ±20 mA
I
out
DC Output Current, per Pin ±25 mA
I
CC
DC Supply Current, V
CC
and GND Pins ±50 mA
P
D
Power Dissipation in Still Air SOIC Package†
TSSOP Package†
500
450
mW
T
stg
Storage Temperature –65 to +150
_C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
(TSSOP or SOIC Package)
260
_C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of
these limits are exceeded, device functionality should not be assumed, damage may occur and
reliability may be affected.
†Derating: SOIC Package: –7 mW/_C from 65_ to 125_C
TSSOP Package: −6.1 mW/°C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
CC
DC Supply Voltage (Referenced to GND) 4.5 5.5 V
V
in
, V
out
DC Input Voltage, Output Voltage (Referenced to GND) 0 V
CC
V
T
A
Operating Temperature, All Package Types –55 +125
_C
t
r
, t
f
Input Rise and Fall Time (Figure 1) 0 500 ns
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, V
in
and
V
out
should be constrained to the
range GND v (V
in
or V
out
) v V
CC
.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V
CC
).
Unused outputs must be left open.
MC74HCT573A
http://onsemi.com
3
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Symbol Parameter Test Conditions
V
CC
V
Guaranteed Limit
Unit
–55 to
25_C
≤ 85_C ≤ 125_C
V
IH
Minimum High−Level Input
Voltage
V
out
= 0.1 V or V
CC
– 0.1 V
|I
out
| ≤ 20 mA
4.5
5.5
2.0
2.0
2.0
2.0
2.0
2.0
V
V
IL
Maximum Low−Level Input
Voltage
V
out
= 0.1 V or V
CC
– 0.1 V
|I
out
| ≤ 20 mA
4.5
5.5
0.8
0.8
0.8
0.8
0.8
0.8
V
V
OH
Minimum High−Level Output
Voltage
V
in
= V
IH
or V
IL
|I
out
| ≤ 20 mA
4.5
5.5
4.4
5.4
4.4
5.4
4.4
5.4
V
V
in
= V
IH
or V
IL
|I
out
| ≤ 6.0 mA 4.5 3.98 3.84 3.7
V
OL
Maximum Low−Level Output
Voltage
V
in
= V
IH
or V
IL
|I
out
| ≤ 20 mA
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
V
V
in
= V
IH
or V
IL
|I
out
| ≤ 6.0 mA 4.5 0.26 0.33 0.4
I
in
Maximum Input Leakage
Current
V
in
= V
CC
or GND 5.5 ±0.1 ±1.0 ±1.0
mA
I
OZ
Maximum Three−State
Leakage Current
Output in High−Impedance State
V
in
= V
IL
or V
IH
V
out
= V
CC
or GND
5.5 ±0.5 ±5.0 ±10
mA
I
CC
Maximum Quiescent Supply
Current (per Package)
V
in
= V
CC
or GND
I
out
≤ 0 mA
5.5 4.0 40 160
mA
ΔI
CC
Additional Quiescent Supply
Current
V
in
= 2.4 V, Any One Input
V
in
= V
CC
or GND, Other Inputs
l
out
= 0 mA
5.5
≥ –55_C 25_C to 125_C
mA
2.9 2.4
AC ELECTRICAL CHARACTERISTICS (V
CC
= 5.0 V ±10%, C
L
= 50 pF, Input t
r
= t
f
= 6.0 ns)
Symbol
Parameter
Guaranteed Limit
Unit
–55 to
25_C
≤ 85_C ≤ 125_C
t
PLH
,
t
PHL
Maximum Propagation Delay, Input D to Output Q
(Figures 1 and 5)
30 38 45 ns
t
PLH
t
PHL
Maximum Propagation Delay, Latch Enable to Q
(Figures 2 and 5)
30 38 45 ns
T
PLZ,
T
PHZ
Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6)
28 35 42 ns
t
TZL,
t
TZH
Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6)
28 35 42 ns
t
TLH
,
t
THL
Maximum Output Transition Time, any Output
(Figures 1 and 5)
12 15 18 ns
C
in
Maximum Input Capacitance 10 10 10 pF
C
out
Maximum Three−State Output Capacitance
(Output in High−Impedance State)
15 15 15 pF
C
PD
Power Dissipation Capacitance (Per Enabled Output)*
Typical @ 25°C, V
CC
= 5.0 V
pF
48
* Used to determine the no−load dynamic power consumption: P
D
= C
PD
V
CC
2
f + I
CC
V
CC
.
TIMING REQUIREMENTS (V
CC
= 5.0 V ±10%, C
L
= 50 pF, Input t
r
= t
f
= 6.0 ns)
Symbol
Parameter Fig.
Guaranteed Limit
Unit
–55 to 25_C ≤ 85_C ≤ 125_C
Min Max Min Max Min Max
t
su
Minimum Setup Time, Input D to Latch Enable 4 10 13 15 ns
t
h
Minimum Hold Time, Latch Enable to Input D 4 5.0 5.0 5.0 ns
t
w
Minimum Pulse Width, Latch Enable 2 15 19 22 ns
t
r
, t
f
Maximum Input Rise and Fall Times 1 500 500 500 ns
P1-P3P4-P6

MC74HCT573ADWR2G

Mfr. #:
Buy MC74HCT573ADWR2G
Manufacturer:
ON Semiconductor
Description:
Latches 5V Octal 3-State Inverter
Lifecycle:
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