7
FN6279.1
November 2, 2007
Component Selection
Because of the fixed internal compensation, the component
choice is relatively narrow. For a regulator with fixed output
voltage, only two capacitors and one inductor are required.
Capacitors must be chosen in the range of 10µF to 40µF,
multilayer ceramic capacitors with X5R or X7R rating for
both the input and output capacitors, and inductors in the
range of 1.5µH to 2.2µH.
The RMS current present at the input capacitor is decided by
Equation 3:
This is about half of the output current I
O
for all the V
O
. This
input capacitor must be able to handle this current.
The inductor peak-to-peak ripple current is given as shown
in Equation 4:
L is the inductance
f
S
the switching frequency (nominally 1.4MHz)
The inductor must be able to handle I
O
for the RMS load
current, and to assure that the inductor is reliable, it must
handle the 2A surge current that can occur during a current
limit condition.
In addition to decoupling capacitors and inductor value, it is
important to properly size the phase-lead capacitor C
4
(Refer to the “Pinout and Typical Application Diagram” on
page 1). The phase-lead capacitor creates additional phase
margin in the control loop by generating a zero and a pole in
the transfer function. As a general rule of thumb, C
4
should
be sized to start the phase-lead at a frequency of ~2.5kHz.
The zero will always appear at lower frequency than the pole
and follow Equation 5:
Over a normal range of R
2
(~10k to100k), C
4
will range from
~470pF to 4700pF. The pole frequency cannot be set once
the zero frequency is chosen as it is dictated by the ratio of
R
1
and R
2
, which is solely determined by the desired output
set point. Equation 6 shows the pole frequency relationship:
Layout Considerations
The layout is very important for the converter to function
properly. The following PC layout guidelines should be
followed:
1. Separate the Power Ground ( ) and Signal Ground
( ); connect them only at one point right at the pins
2. Place the input capacitor as close to V
IN
and PGND pins
as possible
3. Make the following PC traces as small as possible:
- from LX pin to L
- from C
O
to PGND
4. If used, connect the trace from the FB pin to R
1
and R
2
as close as possible
5. Maximize the copper area around the PGND pin
6. Place several via holes under the chip to additional
ground plane to improve heat dissipation
The demo board is a good example of layout based on this
outline.
I
INRMS
V
O
V
IN
V
O
–()×
V
IN
-----------------------------------------------
I
O
×=
(EQ. 3)
ΔI
IL
V
IN
( V
O
) V
O
×–
LV
IN
f
S
××
--------------------------------------------
=
(EQ. 4)
f
Z
1
2πR
2
C
4
----------------------
=
(EQ. 5)
f
P
1
2π R
1
R
2
()C
4
---------------------------------------
=
(EQ. 6)
ISL97536
