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AD7895ARZ-10REEL

P1-P3P4-P6P7-P9P10-P12P13-P13
AD7895
–3–
REV. 0
TIMING CHARACTERISTICS
1, 2
Parameter A, B Versions Units Test Conditions/Comments
t
1
40 ns min CONVST Pulse Width
t
2
35
2
ns min SCLK High Pulse Width
t
3
35
2
ns min SCLK Low Pulse Width
t
4
60
3
ns max Data Access Time after Falling Edge of SCLK, V
DD
= 5 V
±
5%
t
5
10 ns min Data Hold Time after Falling Edge of SCLK
t
6
50
4
ns max Bus Relinquish Time after Falling Edge of SCLK
NOTES
1
Sample tested at +25°C to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of +5 V) and timed from a voltage level of +1.4 V.
2
The SCLK maximum frequency is 15 MHz. Care must be taken when interfacing to account for the data access time, t
4
, and the setup time required for the user's
processor. These two times will determine the maximum SCLK frequency that the user’s system can operate with. See “Serial Interface” section for more information.
3
Measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.0 V.
4
Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back
to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
6
, quoted in the timing characteristics is the true bus relinquish time
of the part and, as such, is independent of external bus loading capacitances.
ABSOLUTE MAXIMUM RATINGS*
(T
A
= +25°C unless otherwise noted)
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Analog Input Voltage to GND
AD7895-10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±17 V
AD7895-2, AD7895-3 . . . . . . . . . . . . . . . . . . . –5 V, +10 V
Reference Input Voltage to GND . . . . –0.3 V to V
DD
+ 0.3 V
Digital Input Voltage to GND . . . . . . . –0.3 V to V
DD
+ 0.3 V
Digital Output Voltage to GND . . . . . –0.3 V to V
DD
+ 0.3 V
Operating Temperature Range
Commercial (A, B Versions) . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Plastic DIP Package, Power Dissipation . . . . . . . . . . 450 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . 130°C/W
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . +260°C
SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . 170°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
WARNING!
ESD SENSITIVE DEVICE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7895 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
(V
DD
= +5 V, GND = 0 V, REF IN = +2.5 V)
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ORDERING GUIDE
Model Temperature Range Linearity Error (LSB) SNR (dB) Package Option*
AD7895AN-2 –40°C to +85°C ±1 LSB 70 dB N-8
AD7895AR-2 –40°C to +85°C ±1 LSB 70 dB SO-8
AD7895BR-2 –40°C to +85°C ±1 LSB 70 dB SO-8
AD7895AN-10 –40°C to +85°C ±1 LSB 70 dB N-8
AD7895AR-10 –40°C to +85°C ±1 LSB 70 dB SO-8
AD7895BR-10 –40°C to +85°C ±1 LSB 70 dB SO-8
AD7895AN-3 –40°C to +125°C ±1 LSB 70 dB N-8
AD7895AR-3 –40°C to +85°C ±1 LSB 70 dB SO-8
*N = Plastic DIP, SO = SOIC.
+1.6V
2.0mA
2.0mA
50pF
TO
OUTPUT
PIN
Figure 1. Load Circuit for Access Time and Bus
Relinquish Time
AD7895
–4–
REV. 0
PIN FUNCTION DESCRIPTION
Pin Pin
No. Mnemonic Description
1 REF IN Voltage Reference Input. An external reference source should be connected to this pin to provide the refer-
ence voltage for the AD7895’s conversion process. The REF IN input is buffered on chip. The nominal ref-
erence voltage for correct operation of the AD7895 is +2.5 V.
2V
IN
Analog Input Channel. The analog input range is ±10 V (AD7895-10), ±2.5 V (AD7895-3) and 0 V to
+2.5 V (AD7895-2).
3 GND Analog Ground. Ground reference for track/hold, comparator, digital circuitry and DAC.
4 SCLK Serial Clock Input. An external serial clock is applied to this input to obtain serial data from the AD7895.
A new serial data bit is clocked out on the falling edge of this serial clock. Data is guaranteed valid for 10 ns
after this falling edge so that data can be accepted on the falling edge when a fast serial clock is used. The
serial clock input should be taken low at the end of the serial data transmission.
5 SDATA Serial Data Output. Serial data from the AD7895 is provided at this output. The serial data is clocked out
by the falling edge of SCLK, but the data can also be read on the falling edge of SCLK. This is possible
because data bit N is valid for a specified time after the falling edge of SCLK (data hold time) (see Figure 4).
Sixteen bits of serial data are provided with four leading zeros followed by the 12 bits of conversion data.
On the sixteenth falling edge of SCLK, the SDATA line is held for the data hold time and then is disabled
(three-stated). Output data coding is 2s complement for the AD7895-10, AD7895-3 and straight binary for
the AD7895-2.
6 BUSY The BUSY pin is used to indicate when the part is doing a conversion. The BUSY pin will go high on the
falling edge of
CONVST and will return low when the conversion is complete.
7
CONVST Convert Start. Edge-triggered logic input. On the falling edge of this input, the track/hold goes into its hold
mode, and conversion is initiated. If
CONVST is low at the end of conversion, the part goes into power-
down mode. In this case, the rising edge of
CONVST “wakes up” the part.
8V
DD
Positive supply voltage, +5 V ± 5%.
PIN CONFIGURATION
DIP and SOIC
1
2
3
4
8
7
6
5
TOP VIEW
(Not to Scale)
AD7895
REF IN
SDATA
BUSY
CONVST
V
DD
V
IN
GND
SCLK
AD7895
–5–
REV. 0
TERMINOLOGY
Signal to (Noise + Distortion) Ratio
This is the measured ratio of signal to (noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the rms sum of all nonfundamental
signals up to half the sampling frequency (f
S
/2), excluding dc.
The ratio is dependent upon the number of quantization levels
in the digitization process; the more levels, the smaller the
quantization noise. The theoretical signal to (noise + distortion)
ratio for an ideal N-bit converter with a sine wave input is given
by:
Signal to (Noise + Distortion) = (6.02 N + 1.76) dB
Thus for a 12-bit converter, this is 74 dB.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7895, it is defined as:
THD (dB)= 20 log
V
2
2
+V
3
2
+V
4
2
+V
5
2
+V
6
2
V
1
where V
1
is the rms amplitude of the fundamental, and V
2
, V
3
,
V
4
, V
5
and V
6
are the rms amplitudes of the second through the
sixth harmonics.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to f
S
/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is
determined by the largest harmonic in the spectrum, but for
parts where the harmonics are buried in the noise floor, it will
be a noise peak.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which
neither m or n are equal to zero. For example, the second order
terms include (fa + fb) and (fa – fb), while the third order terms
include (2 fa + fb), (2 fa – fb), (fa + 2 fb) and (fa – 2 fb).
The AD7895 is tested using the CCIF standard where two
input frequencies near the top end of the input bandwidth are
used. In this case, the second and third order terms are of
different significance. The second order terms are usually
distanced in frequency from the original sine waves, while the
third order terms are usually at a frequency close to the input
frequencies. As a result, the second and third order terms are
specified separately. The calculation of the intermodulation
distortion is as per the THD specification where it is the ratio of
the rms sum of the individual distortion products to the rms
amplitude of the fundamental expressed in dBs.
Relative Accuracy
Relative accuracy or endpoint nonlinearity is the maximum
deviation from a straight line passing through the endpoints of
the ADC transfer function.
Differential Nonlinearity
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Positive Full-Scale Error (AD7895-10)
This is the deviation of the last code transition (01 . . . 110 to
01 . . . 111) from the ideal (4 × VREF – 1 LSB) after the
Bipolar Zero Error has been adjusted out.
Positive Full-Scale Error (AD7895-3)
This is the deviation of the last code transition (01 . . . 110 to
01 . . . 111) from the ideal ( VREF – 1 LSB) after the
Bipolar Zero Error has been adjusted out.
Positive Full-Scale Error (AD7895-2)
This is the deviation of the last code transition (11 . . . 110 to
11 . . . 111) from the ideal (VREF – 1 LSB) after the Unipolar
Offset Error has been adjusted out.
Bipolar Zero Error (AD7895-10, AD7895-3)
This is the deviation of the midscale transition (all 0s to all 1s)
from the ideal 0 V (GND).
Unipolar Offset Error (AD7895-2)
This is the deviation of the first code transition (00 . . . 000 to
00 . . . 001) from the ideal 1 LSB.
Negative Full-Scale Error (AD7895-10)
This is the deviation of the first code transition (10 . . . 000 to
10 . . . 001) from the ideal (–4 × VREF + 1 LSB) after Bipolar
Zero Error has been adjusted out.
Negative Full-Scale Error (AD7895-3)
This is the deviation of the first code transition (10 . . . 000 to
10 . . . 001) from the ideal (–VREF + 1 LSB) after Bipolar Zero
Error has been adjusted out.
Track/Hold Acquisition Time
Track/Hold acquisition time is the time required for the output
of the track/hold amplifier to reach its final value, within
±1/2 LSB, after the end of conversion (the point at which the
track/hold returns to track mode). It also applies to situations
where there is a step input change on the input voltage applied
to the V
IN
input of the AD7895. This means that the user must
wait for the duration of the track/hold acquisition time after the
end of conversion or after a step input change to V
IN
before
starting another conversion to ensure that the part operates to
specification.
P1-P3P4-P6P7-P9P10-P12P13-P13

AD7895ARZ-10REEL

Mfr. #:
Buy AD7895ARZ-10REEL
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC Bipolar Input 5V 12B Serial 3.8uS
Lifecycle:
New from this manufacturer.
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