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ICS525RI-11LFT

P1-P3P4-P6P7-P9
ICS525-01/02
USER CONFIGURABLE CLOCK CLOCK MULTIPLIER
IDT®
USER CONFIGURABLE CLOCK 4
ICS525-01/02 REV U 033015
External Components/Crystal
Selection
Decoupling Capacitors
The ICS525-01/02 requries two 0.01µF decoupling
capacitors to be connected between VDD and GND,
one on each side of the chip. The capacitor must be
connected close to the device to minimize lead
inductance.
External Resistors
A 33series termination resistor should be used on the
CLK and REF pins.
Crystal Load Capacitors
The approximate total on-chip capacitance for a crystal
is 16 pF, so a parallel resonant, fundamental mode
crystal with this value of load (correlation) capacitance
should be used. For crystals with a specified load
capacitance greater than 16 pF, crystal capacitors may
be connected from each of the pins X1 and X2 to
Ground as shown in the block diagram. The value (in
pF) of these crystal caps should be (CL -16)*2, where
CL is the crystal load capacitance in pF. These external
capacitors are only required for applications where the
exact frequency is critical. For a clock input, connect to
X1 and leave X2 unconnected (no capacitors on either).
Determining the Output Frequency
Users have full control in setting the desired output
frequency over the range shown in the tables on pages
3-4. To replace a standard oscillator, users should
connect the divider select input pins directly to ground
(or VDD, although this is not required because of
internal pull-ups) during Printed Circuit Board layout.
The ICS525 will automatically produce the correct
frequency when all components are soldered. It is also
possible to connect the inputs to parallel I/O ports to
switch frequencies. By choosing divides carefully, the
number of inputs which need to be changed can be
minimized. Observe the restrictions on allowed values
of VDW and RDW.
Configuration Pin Settings
The output of the ICS525 can be determined by the
following simple equation:
Where:
Reference Divider Word (RDW) = 0 to 127 (0 not
permitted for ICS525-01)
VCO Divider Word (VDW) = 0 to 511 (0, 1, 2, 3 not
permitted for ICS525-01)
Output Divider (OD) = values on pages 3-4
Also, the following operating ranges should be
observed:
1. The output frequency must be in the ranges listed on
pages 3-4.
2. The phase detector frequency must be above 200
kHz.
Since all of the inputs have pull-up resistors, it is only
necessary to ground the pins that need to be set to zero.
Which Part to Use?
The ICS525-01 is the original configurable clock.
The ICS525-02 has a higher maximum output
grequency and a slightly different set of output dividers.
To determine the best combination of VCO, reference,
and output divide, use the ICS525 Calculator on our
web site.
CLK Frequency Input Frequency 2x
VDW 8+
RDW 2+OD
---------------------------------------------
=
200kHz
InputFrequency
RDW 2+
-----------------------------------------------<
ICS525-01/02
USER CONFIGURABLE CLOCK CLOCK MULTIPLIER
IDT®
USER CONFIGURABLE CLOCK 5
ICS525-01/02 REV U 033015
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS525-01/02. These ratings,
which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V
Item Rating
Supply Voltage, VDD 7 V
All Inputs and Outputs -0.5 V to VDD+0.5 V
Ambient Operating Temperature, Commercial 0 to +70C
Ambient Operating Temperature, Industrial -40 to +85C
Storage Temperature -65C to 150C
Junction Temperature 125C
Soldering Temperature 260C (max. of 10 seconds)
Parameter Symbol Conditions Min. Typ. Max. Units
Operating Voltage VDD 3.0 5.5 V
Operating Supply Current IDD 60 MHz out, no load,
15 MHz crystal,
ICS525-01/02 only
8mA
Operating Supply Current,
Power-down
IDD Pin 19 = 0, Note 1 4 µA
Input High Voltage V
IH
2V
Input Low Voltage V
IL
0.8 V
Input High Voltage,
X1/ICLK only
V
IH
ICLK (pin7)
VDD/2+1
VDD/2 V
Input Low Voltage, X1/ICLK
only
V
IL
ICLK (pin7) VDD/2
VDD/2-1
V
Output High Voltage V
OH
I
OH
= -12 mA
VDD-0.4
V
Output Low Voltage V
OL
I
OL
= 12 mA 0.4 V
Short Circuit Current CLK and REF outputs ±55 mA
Input Capacitance C
IN
V, R, S pins and pin 19 4 pF
On-chip Pull-up Resistor R
PU
V, R, S pins and pin 19 270 k
ICS525-01/02
USER CONFIGURABLE CLOCK CLOCK MULTIPLIER
IDT®
USER CONFIGURABLE CLOCK 6
ICS525-01/02 REV U 033015
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V
NOTE 1: Phase relationship between input and output can change at power-up. For a fixed phase
relationship, see the ICS527.
NOTE 2: For 16 MHz, 100 MHz output. Use the -02 for lowest jitter.
Parameter Symbol Conditions Min. Typ. Max. Units
Input Frequency F
IN
Crystal input 5 27 MHz
Clock input 2 50 MHz
Output Clock Rise Time 0.8 to 2.0 V 1 ns
Output Clock Fall Time 2.0 to 0.8 V 1 ns
Output Clock Duty Cycle, OD =
2, 4, 6, 8, or 10
At VDD/2 45
49 to
51
55 %
Output Clock Duty Cycle, OD =
3, 5, 7, or 9
At VDD/2 40 60 %
Output Clock Duty Cycle, OD =
1 (-02 only)
At VDD/2 35 65
Power-down Time, PD low to
clocks stopped
50 ns
Power-up Time, PD high to
clocks stable
10 ms
Absolute Clock Period Jitter,
ICS525-01, Note 2
t
ja
Deviation from mean ±140 ps
One Sigma Clock Period Jitter,
ICS525-01, Note 2
t
js
One Sigma 45 ps
Absolute Clock Period Jitter,
ICS525-02, Note 2
t
ja
Deviation from mean ±85 ps
One Sigma Clock Period Jitter,
ICS525-02, Note 2
t
js
One Sigma 30 ps
P1-P3P4-P6P7-P9

ICS525RI-11LFT

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IC PECL CLK USER CONFIG 28-SSOP
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