4
LTC1477/LTC1478
LTC1477
EN (Pin 4): The enable input is a high impedance CMOS
gate with an ESD protection diode to ground and should
not be forced below ground. This input has about 100mV
of built-in hysteresis to ensure clean switching.
V
INS
, V
IN1
(Pins 3,2): The V
INS
supply pin must always be
connected to the V
IN1
supply pin (see Block Diagram). The
V
INS
supply pin provides power for the input control logic,
the current limit and thermal shutdown circuitry; plus
provides a sense connection to the input power supply.
The gate of the NMOS switch is powered by a charge pump
from the V
INS
supply pin (see Block Diagram). The V
IN1
supply pin provides connection to the drain of 1/2 of the
output power device.
V
IN2
, V
IN3
(Pins 7,6): The V
IN2
and V
IN3
supply pins are
typically tied to the V
INS
and V
IN1
supply pins for lowest ON
resistance; i.e., when all four V
IN
pins are connected
together the entire power device is connected (see Block
Diagram). Each auxiliary supply pin, V
IN2
and V
IN3
, is
connected to the drain of 1/4 of the power device. The V
IN2
and V
IN3
pins can be selectively disconnected to reduce
the short-circuit current limit at the expense of higher
R
DS(ON)
. (See Applications Information section for more
details.)
V
OUT
(Pins 1,8): The output pins of the LTC1477 must
always be tied together. The output is protected against
accidental short circuits to ground by a current limit circuit
which protects the system power supply and load against
damage. A second level of protection is provided by
thermal shutdown circuitry which limits the die tempera-
ture to 130°C.
LTC1478
AEN, BEN (Pins 4,12): The enable inputs are high imped-
ance CMOS gates with ESD protection diodes to ground
and should not be forced below ground. These inputs
have about 100mV of built-in hysteresis to ensure clean
switching.
AV
INS
, AV
IN1
, BV
INS
, BV
IN1
(Pins 3,2; 11,10): The AV
INS
or BV
INS
supply pin must always be connected to the
AV
IN1
or BV
IN1
supply pin (see Block Diagram). The AV
INS
and BV
INS
supply pins provide power for the input control
logic, the current limit and thermal shutdown circuitry;
plus, provides a sense connection to the input power
supply. The gate of the NMOS switch is powered by a
charge pump from the AV
INS
and BV
INS
supply pins (see
Block Diagram). The AV
IN1
and BV
IN1
supply pins provide
connection to the drain of 1/2 of the output power device.
AV
IN2
, AV
IN3
, BV
IN2
, BV
IN3
, (Pins 15,14; 7,6): The AV
IN2
,
AV
IN3
, BV
IN2
and BV
IN3
supply pins are typically tied to the
AV
INS
, AV
IN1
, BV
INS
and BV
IN1
supply pins for lowest ON
resistance; i.e., when all four AV
IN
, BV
IN
pins are con-
nected together the entire power device is connected (see
Block Diagram). Each auxiliary supply pin, AV
IN2
, AV
IN3
,
BV
IN2
and BV
IN3
, is connected to the drain of approxi-
mately 1/4 of the corresponding power device. The AV
IN2
,
AV
IN3
, BV
IN2
and BV
IN3
pins can be selectively discon-
nected to reduce the short-circuit current limit at the
expense of higher R
DS(ON)
. (See Applications Information
section for more details.)
AV
OUT
, BV
OUT
(Pins 1,16; 8,9): The outputs of the LTC1478
are protected against accidental short circuits to ground
by a current limit circuit which protects the system power
supplies and loads against damage. A second level of
protection is provided by thermal shutdown circuitry
which limits the die temperature to approximately 130°C.
PIN FUNCTIONS
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