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LTC1478CS#PBF

P1-P3P4-P6P7-P8
4
LTC1477/LTC1478
LTC1477
EN (Pin 4): The enable input is a high impedance CMOS
gate with an ESD protection diode to ground and should
not be forced below ground. This input has about 100mV
of built-in hysteresis to ensure clean switching.
V
INS
, V
IN1
(Pins 3,2): The V
INS
supply pin must always be
connected to the V
IN1
supply pin (see Block Diagram). The
V
INS
supply pin provides power for the input control logic,
the current limit and thermal shutdown circuitry; plus
provides a sense connection to the input power supply.
The gate of the NMOS switch is powered by a charge pump
from the V
INS
supply pin (see Block Diagram). The V
IN1
supply pin provides connection to the drain of 1/2 of the
output power device.
V
IN2
, V
IN3
(Pins 7,6): The V
IN2
and V
IN3
supply pins are
typically tied to the V
INS
and V
IN1
supply pins for lowest ON
resistance; i.e., when all four V
IN
pins are connected
together the entire power device is connected (see Block
Diagram). Each auxiliary supply pin, V
IN2
and V
IN3
, is
connected to the drain of 1/4 of the power device. The V
IN2
and V
IN3
pins can be selectively disconnected to reduce
the short-circuit current limit at the expense of higher
R
DS(ON)
. (See Applications Information section for more
details.)
V
OUT
(Pins 1,8): The output pins of the LTC1477 must
always be tied together. The output is protected against
accidental short circuits to ground by a current limit circuit
which protects the system power supply and load against
damage. A second level of protection is provided by
thermal shutdown circuitry which limits the die tempera-
ture to 130°C.
LTC1478
AEN, BEN (Pins 4,12): The enable inputs are high imped-
ance CMOS gates with ESD protection diodes to ground
and should not be forced below ground. These inputs
have about 100mV of built-in hysteresis to ensure clean
switching.
AV
INS
, AV
IN1
, BV
INS
, BV
IN1
(Pins 3,2; 11,10): The AV
INS
or BV
INS
supply pin must always be connected to the
AV
IN1
or BV
IN1
supply pin (see Block Diagram). The AV
INS
and BV
INS
supply pins provide power for the input control
logic, the current limit and thermal shutdown circuitry;
plus, provides a sense connection to the input power
supply. The gate of the NMOS switch is powered by a
charge pump from the AV
INS
and BV
INS
supply pins (see
Block Diagram). The AV
IN1
and BV
IN1
supply pins provide
connection to the drain of 1/2 of the output power device.
AV
IN2
, AV
IN3
, BV
IN2
, BV
IN3
, (Pins 15,14; 7,6): The AV
IN2
,
AV
IN3
, BV
IN2
and BV
IN3
supply pins are typically tied to the
AV
INS
, AV
IN1
, BV
INS
and BV
IN1
supply pins for lowest ON
resistance; i.e., when all four AV
IN
, BV
IN
pins are con-
nected together the entire power device is connected (see
Block Diagram). Each auxiliary supply pin, AV
IN2
, AV
IN3
,
BV
IN2
and BV
IN3
, is connected to the drain of approxi-
mately 1/4 of the corresponding power device. The AV
IN2
,
AV
IN3
, BV
IN2
and BV
IN3
pins can be selectively discon-
nected to reduce the short-circuit current limit at the
expense of higher R
DS(ON)
. (See Applications Information
section for more details.)
AV
OUT
, BV
OUT
(Pins 1,16; 8,9): The outputs of the LTC1478
are protected against accidental short circuits to ground
by a current limit circuit which protects the system power
supplies and loads against damage. A second level of
protection is provided by thermal shutdown circuitry
which limits the die temperature to approximately 130°C.
PIN FUNCTIONS
UUU
5
LTC1477/LTC1478
OPERATION
U
(LTC1477 or single channel of LTC1478)
Input TTL-CMOS Converter
The LTC1477 enable input is designed to accommodate a
wide range of 3V and 5V logic families. The input threshold
voltage is approximately 1.4V with 100mV of hysteresis.
The input enables the bias generator, the gate charge
pump and the protection circuitry. Therefore, when the
enable input is turned off, the entire circuit is powered
down and the supply current drops below 1µA.
Ramped Switch Control
The LTC1477 gate charge pump includes circuitry which
ramps the NMOS switch on slowly (1ms typical rise time)
but turns it off much more quickly (typically 20µs).
Bias, Oscillator and Gate Charge Pump
When the switch is enabled, a bias current generator and
high frequency oscillator are turned on. The on-chip
capacitive charge pump generates approximately 12V of
gate drive for the internal low R
DS(ON)
NMOS switch from
the power supply. No external 12V supply is required to
switch the output.
Switch Protection
Two levels of protection are designed into the power
switch in the LTC1477. The switch is protected against
accidental short circuits with a current limit circuit which
limits the output current to typically 2A when the output is
shorted to ground. The LTC1477 also has thermal shut-
down set at approximately 130°C which limits the power
dissipation to safe levels.
LTC1478 Operation
The LTC1478 dual protected switch can be thought of as
two independent LTC1477 single protected switches. The
input supply voltages may be from separate power sources.
The ground connection, however, is common to both
channels and must be connected to the same potential.
(LTC1477 or single channel of LTC1478)
BLOCK DIAGRAM
W
APPLICATIONS INFORMATION
WUU
U
Table 1. Effects of Disconnecting V
IN2
and V
IN3
ALL V
IN
PINS V
IN3
V
IN2
AND V
IN3
CONNECTED DISCONNECTED DISCONNECTED
R
DS(ON)
0.07Ω 0.09Ω 0.12Ω
I
LIMIT
2A 1.5A 0.85A
Note: 5V Operation
Note that there is an inverse relationship between output
current limit and switch resistance. This allows the tailor-
TTL-TO-CMOS
CONVERTER
OSCILLATOR
AND BIAS
CHARGE
PUMP
GATE CHARGE
AND
DISCHARGE
CONTROL LOGIC
CURRENT LIMIT
AND THERMAL
SHUTDOWN
EN
V
INS
V
IN1
V
IN2
V
IN3
V
OUT
LTC1477/1478 • BD01
Tailoring I
LIMIT
and R
DS(ON)
for Load Requirements
The LTC1477 is designed to current limit at approximately
2A during a short circuit with all the V
IN
pins connected to
the input power supply. It is possible however, to reduce
this current by selectively disconnecting two of the four
power supply pins (V
IN2
and V
IN3
). Table 1 lists the effects
of disconnecting these pins on R
DS(ON)
and short-circuit
current limit
6
LTC1477/LTC1478
APPLICATIONS INFORMATION
WUU
U
ing of the switch parameters to the expected load current
and system current limit requirements.
A couple of examples are helpful:
1. If a nominal load of 1A was controlled by the switch
configured to current limit at 2A (all V
IN
pins connected
together), the R
DS(ON)
would be 0.07Ω and the voltage
drop across the switch would be 70mV. The power
dissipated by the switch would only be 70mW.
2. If a nominal load of 0.5A was controlled by the switch
configured to current limit at 0.85A (V
IN2
and V
IN3
disconnected), the R
DS(ON)
would increase to 0.14Ω.
But the voltage drop would remain at 70mV and the
switch power dissipation would drop to 35mW.
Supply Bypassing
For best results, bypass the supply input pins with a single
1.0µF capacitor as close as possible to the LTC1477.
Sometimes, much larger capacitors are already available
at the output of the power supply. In this case, it is still
good practice to use a 0.1µF capacitor as close as possible
to the LTC1477, especially if the power supply output
capacitor is more than 2 inches away on the printed circuit
board.
Output Capacitor
The output pin is designed to ramp on slowly, typically
1ms rise time. Therefore, very large output capacitors can
be driven without producing voltage spikes on the supply
pins (see graphs in Typical Performance Characteristics).
The output pin should have a 1µF capacitor for noise
reduction and smoothing.
Supply and Input Sequencing
The LTC1477 is designed to operate with continuous
power (quiescent current drops to < 1µA when disabled).
If the power must be turned off, for example to enter a
system “sleep” mode, the enable input must be turned off
100µs before the input supply is turned off to ensure that
the gate of the NMOS switch is completely discharged
before power is removed. However, the input control and
power can be applied simultaneously during power up.
TYPICAL APPLICATIONS
U
0.85A Protected Switch 2A Protected Switch Driving a Large Capacitive Load
+
C
LOAD
100µF
0.1µF
LTC1477/1478 • TA06
ON/OFF
2.7V TO 5.5V
LTC1477
V
OUT
V
IN2
V
IN3
GND
V
OUT
V
IN1
V
INS
EN
V
OUT
+
1µF
0.1µF
LTC1477/1478 • TA05
ON/OFF
2.7V TO 5.5V
I
SC
= 0.85A
NC
NC
LTC1477
V
OUT
V
IN2
V
IN3
GND
V
OUT
V
IN1
V
INS
EN
+
1µF
0.1µF
LTC1477/1478 • TA04
ON/OFF
2.7V TO 5.5V
I
SC
= 1.5A
NC
LTC1477
V
OUT
V
IN2
V
IN3
GND
V
OUT
V
IN1
V
INS
EN
2A Protected Switch 1.5A Protected Switch
+
1µF
0.1µF
LTC1477/1478 • TA03
ON/OFF
2.7V TO 5.5V
I
SC
= 2A
V
OUT
V
IN2
V
IN3
GND
V
OUT
V
IN1
V
INS
EN
LTC1477
P1-P3P4-P6P7-P8

LTC1478CS#PBF

Mfr. #:
Buy LTC1478CS#PBF
Manufacturer:
Analog Devices / Linear Technology
Description:
Gate Drivers Dual Protected High-Side Switch
Lifecycle:
New from this manufacturer.
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