REVISION B 10/29/15 13 FEMTOCLOCK
®
CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR
843251I-15 DATA SHEET
Schematic Example
Figure 6 shows an example of 843251I-15 application schematic. In
this example, the device is operated at V
CC
= 3.3V. The 18pF
parallel resonant 25MHz crystal is used. The C1 = 27pF and C2 =
27pF are recommended for frequency accuracy. For different board
layout, the C1 and C2 may be slightly adjusted for optimizing
frequency accuracy. Two examples of LVPECL termination are
shown in this schematic. Additional termination approaches are
shown in the LVPECL Termination Application Note.
Note: Thermal pad (E-pad) must be connected to ground (V
EE
).
Figure 6. 843251I-15 Schematic Example
VC C
VCC A
C4
10uF
C5
0.01 u
Zo = 50 O hm
R3
133
To Lo g ic
Input
pin s
Zo = 50 O hm
VCC
Set Logic
Input to
'0'
FREQ_SEL
VCC=3.3V
C1
27pF
C3
0.01u
Q
Zo = 50 O hm
RD 1
Not Install
R1
10
XTAL_IN
R7
50
Opt ional
Y-Terminat ion
To Logic
Input
pins
XTAL_OU T
3.3V
X1
25MHz
RD2
1K
VCC
VCC
VCC
U1
1
2
3
4
8
7
6
5
VCCA
VEE
XTAL_OU T
XTAL_IN
VCC
Q
nQ
FREQ_SEL
R2
133
Logic Cont rol Input Examples
RU2
Not Install
R5
82.5
RU 1
1K
nQ
C2
27pF
R4
82.5
R8
50
Zo = 50 O hm
+
-
R6
50
Set Logic
Input to
'1'
+
-
FEMTOCLOCK
®
CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR 14 REVISION B 10/29/15
843251I-15 DATA SHEET
Power Considerations
This section provides information on power dissipation and junction temperature for the 843251I-15.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the 843251I-15 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
CC
= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX
= V
CC_MAX
* I
EE_MAX
= 3.465V * 83mA = 287.60mW
Power (outputs)
MAX
= 30mW/Loaded Output pair
Total Power_
MAX
(3.3V, with all outputs switching) = 287.60mW + 30mW = 317.60mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device.
The maximum recommended junction temperature is 125°C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used. Assuming a moderate
air flow of 1 meter per second and a multi-layer board, the appropriate value is 125.5°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.318W * 125.5°C/W = 124.9°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type
of board (multi-layer).
Table 6. Thermal Resistance
JA
for 8 Lead TSSOP, Forced Convection
JA
vs. Air Flow
Meters per Second 012.5
Multi-Layer PCB, JEDEC Standard Test Boards 129.5°C/W 125.5°C/W 123.5°C/W
REVISION B 10/29/15 15 FEMTOCLOCK
®
CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR
843251I-15 DATA SHEET
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 7.
Figure 7. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage
of V
CC
– 2V.
For logic high, V
OUT
= V
OH_MAX
= V
CC_MAX
– 0.9V
(V
CC_MAX
– V
OH_MAX
) = 0.9V
For logic low, V
OUT
= V
OL_MAX
= V
CC_MAX
1.7V
(V
CC_MAX
– V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
– (V
CC_MAX
– 2V))/R
L
] * (V
CC_MAX
– V
OH_MAX
) = [(2V – (V
CC_MAX
– V
OH_MAX
))/R
L
] * (V
CC_MAX
– V
OH_MAX
) =
[(2V – 0.9V)/50] * 0.9V = 19.8mW
Pd_L = [(V
OL_MAX
– (V
CC_MAX
– 2V))/R
L
] * (V
CC_MAX
– V
OL_MAX
) = [(2V – (V
CC_MAX
– V
OL_MAX
))/R
L]
* (V
CC_MAX
– V
OL_MAX
) =
[(2V – 1.7V)/50] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
V
OUT
V
CC
V
CC
- 2V
Q1
RL
50Ω

843251BGI-15LF

Mfr. #:
Manufacturer:
Description:
IC CLOCK GENERATOR 750MHZ 8TSSOP
Lifecycle:
New from this manufacturer.
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