AD8061/AD8062/AD8063 Data Sheet
Rev. J | Page 16 of 20
CAPACITIVE LOAD DRIVE
The AD8061/AD8062/AD8063 family is optimized for
bandwidth and speed, not for driving capacitive loads. Output
capacitance creates a pole in the amplifier’s feedback path,
leading to excessive peaking and potential oscillation. If dealing
with load capacitance is a requirement of the application, the
two strategies to consider are as follows:
Use a small resistor in series with the amplifier’s output and the
load capacitance.
Reduce the bandwidth of the amplifier’s feedback loop by
increasing the overall noise gain.
Figure 50 shows a unity-gain follower using the series resistor
strategy. The resistor isolates the output from the capacitance
and, more importantly, creates a zero in the feedback path that
compensates for the pole created by the output capacitance.
AD8061
V
O
R
SERIES
C
LOAD
V
IN
01065-050
Figure 50. Series Resistor Isolating Capacitive Load
Voltage feedback amplifiers like those in the AD8061/AD8062/
AD8063 family are able to drive more capacitive load without
excessive peaking when used in higher gain configurations
because the increased noise gain reduces the bandwidth of the
overall feedback loop. Figure 51 plots the capacitance that
produces 30% overshoot vs. noise gain for a typical amplifier.
CLOSED-LOOP GAIN
10k
1k
10
1 52
CA
PACITIVE LOAD (pF)
100
3 4
R
S
= 0
R
S
= 4.7
01065-051
Figure 51. Capacitive Load vs. Closed-Loop Gain
DISABLE OPERATION
The internal circuit for the AD8063 disable function is shown
in Figure 52. When the
DISABLE
node is pulled below 2 V
from the positive supply, the supply current decreases from
typically 6.5 mA to under 400 µA, and the AD8063 output
enters a high impedance state. If the
DISABLE
node is not
connected and allowed to float, the AD8063 stays biased at
full power.
VCC
DISABLE
T
O AMPLIFIER
BIAS
VEE
2V
01065-052
Figure 52. Disable Circuit of the AD8063
Figure 34 shows the AD8063 supply current vs.
DISABLE
voltage. Figure 35 plots the output seen when the AD8063 input
is driven with a 10 MHz sine wave, and
DISABLE
is toggled
from 0 V to 5 V, illustrating the parts turn-on and turn-off
time. Figure 33 shows the input/output isolation response with
the AD8063 shut off.
BOARD LAYOUT CONSIDERATIONS
Maintaining the high speed performance of the AD8061/AD8062/
AD8063 family requires the use of high speed board layout
techniques and low parasitic components.
The PCB should have a ground plane covering unused portions
of the component side of the board to provide a low impedance
path. Remove the ground plane near the package to reduce
parasitic capacitance.
Proper bypassing is critical. Use a ceramic 0.1 µF chip capacitor
to bypass both supplies. Locate the chip capacitor within 3 mm
of each power pin. Additionally, connect in parallel a 4.7 µF to
10 µF tantalum electrolytic capacitor to provide charge for fast,
large signal changes at the output.
Minimizing parasitic capacitance at the amplifiers inverting
input pin is very important. Locate the feedback resistor close to
the inverting input pin. The value of the feedback resistor may
come into playfor instance, 1 kΩ interacting with 1 pF of
parasitic capacitance creates a pole at 159 MHz. Use stripline
design techniques for signal traces longer than 25 mm. Design
them with either 50 Ω or 75 Ω characteristic impedance and
proper termination at each end.
Data Sheet AD8061/AD8062/AD8063
Rev. J | Page 17 of 20
APPLICATIONS INFORMATION
SINGLE-SUPPLY SYNC STRIPPER
When a video signal contains synchronization pulses, it is
sometimes desirable to remove them prior to performing
certain operations. In the case of analog-to-digital conversion,
the sync pulses consume some of the dynamic range, so
removing them increases the converter’s available dynamic
range for the video information.
Figure 53 shows a basic circuit for creating a sync stripper using
the AD8061 powered by a single supply. When the negative
supply is at ground potential, the lowest potential to which the
output can go is ground. This feature is exploited to create a
waveform whose lowest amplitude is the black level of the video
and does not include the sync level.
75Ω
VIDEO OUT
75Ω
R
G
1kΩ
75Ω
R
F
1kΩ
10µF
3V
AD8061
0.1µF
3
2
4
6
7
VIDEO IN
PIN NUMBERS ARE
FOR 8-LEAD
PACKAGE
01065-053
Figure 53. Single 3 V Sync Stripper Using AD8061
In this case, the input video signal has its black level at ground,
so it comes out at ground at the input. Because the sync level is
below the black level, it does not show up at the output. However,
all of the active video portion of the waveform is amplified by a
gain of 2 and then normalized to unity gain by the back-
terminated transmission line. Figure 54 is an oscilloscope plot
of the input and output waveforms.
01065-054
500mV
INPUT
OUTPUT
1
2
10µs
Figure 54. Input and Output Waveforms for a Single-Supply
Video Sync Stripper Using an AD8061
Some video signals with sync are derived from single-supply
devices, such as video DACs. These signals can contain sync,
but the whole waveform is positive, and the black level is not
at ground but at a positive voltage.
The circuit can be modified to provide the sync stripping
function for such a waveform. Instead of connecting R
G
to
ground, connect it to a dc voltage that is two times the black
level of the input signal. The gain from the noninverting input
to the output is 2, which means the black level is amplified by 2
to the output. However, the gain through R
G
is −1 to the output.
It takes a dc level of twice the input black level to shift the black
level to ground at the output. When this occurs, the sync is
stripped, and the active video is passed as in the ground-
referenced case.
75Ω
10µF
0.1µF
3V
3
2
4
6
7
75Ω
MONITOR
#1
75Ω
75Ω
75Ω
1kΩ
1kΩ
1kΩ
1kΩ
3V
1kΩ
3
2
5
6
7
8
1
4
MONITOR
#2
GREEN
DAC
RED
GREEN
BLUE
RED
DAC
BLUE
DAC
75Ω
75Ω
75Ω
75Ω
AD8061
75Ω
10µF
0.1µF
1kΩ
AD8062
75Ω
AD8062
75Ω
01065-055
Figure 55. RGB Cable Driver Using AD8061 and AD8062
RGB AMPLIFIER
Most RGB graphics signals are created by video DAC outputs
that drive a current through a resistor to ground. At the video
black level, the current goes to zero, and the voltage of the video
is also zero. Before the availability of high speed rail-to-rail op
amps, it was essential that an amplifier have a negative supply
to amplify such a signal. Such an amplifier is necessary if one
wants to drive a second monitor from the same DAC outputs.
However, high speed, rail-to-rail output amplifiers like the
AD8061 and AD8062 accept ground-level input signals and
output ground-level signals. They are used as RGB signal
amplifiers. A combination of the AD8061 (single) and the
AD8062 (dual) amplifies the three video channels of an RGB
system. Figure 55 shows a circuit that performs this function.
AD8061/AD8062/AD8063 Data Sheet
Rev. J | Page 18 of 20
MULTIPLEXER
The AD8063 has a disable pin used to power down the ampli-
fier to save power or to create a mux circuit. If two (or more)
AD8063 outputs are connected together, and only one is enabled,
then only the signal of the enabled amplifier will appear at the
output. This configuration is used to select from various input
signal sources. Additionally, the same input signal is applied to
different gain stages, or differently tuned filters, to make a gain-
step amplifier or a selectable frequency amplifier.
Figure 56 shows a schematic of two AD8063 devices used to
create a mux that selects between two inputs. One of these is a
1 V p-p, 3 MHz sine wave; the other is a 2 V p-p, 1 MHz sine wave.
49.9Ω
1kΩ
+4V
1
–4V
49.9Ω
TIME
BASE
OUT
TIME
BASE
IN
1V p-p
3MHz
2V p-p
1MHz
V
OUT
49.9Ω
SELECT
HCO4
1kΩ
10µF
0.1µF
10µF
0.1µF
AD8063
49.9
Ω
1kΩ
+4V
1
4V
1k
Ω
10µF
0.1µF
10µF
0.1µF
AD8063
01065-056
Figure 56. Two-to-One Multiplexer Using Two AD8063s
The select signal and the output waveforms for this circuit are
shown in Figure 57. For synchronization clarity, two different
frequency synthesizers, whose time bases are locked to each
other, generate the signals.
1V
2V
2µs
SELECT
OUTPUT
01065-057
Figure 57. AD8063 Mux Output

AD8061ARZ-REEL7

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
High Speed Operational Amplifiers 300MHz RR SGL
Lifecycle:
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