CY25403/CY25423/CY25483
Three-PLL Programmable Clock Generator
with Spread Spectrum
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 001-12564 Rev. *K Revised October 31, 2017
Three-PLL Progr ammable Clock Generator with Spread Spectrum
Features
■ Three fully integrated phase-locked loops (PLLs)
■ Input frequency range
❐ External crystal: 8 to 48 MHz
❐ External reference: 8 to 166 MHz clock
■ Reference clock input voltage range
❐ 2.5 V, 3.0 V, and 3.3 V for CY25483
❐ 1.8 V for CY25403 and CY25423
■ Wide operating output frequency range
❐ 3 to 166 MHz
■ Programmable spread spectrum with center and down spread
option and lexmark and linear modulation profiles
■ V
DD
supply voltage options
❐ 2.5 V, 3.0 V, and 3.3 V for CY25403 and CY25483
❐ 1.8 V for CY25423
■ Frequency select feature with option to select four different
frequencies
■ Power-down, output enable, and SS ON/OFF controls
■ Low jitter, high accuracy outputs
■ Ability to synthesize nonstandard frequencies with Fractional-N
capability
■ Three clock outputs with programmable drive strength
■ Glitch-free outputs while frequency switching
■ 8-pin SOIC package
■ Commercial and Industrial temperature ranges
■ One-time programmability
For programming support, contact Cypress technical support
or send an e-mail to clocks@cypress.com
Benefits
■ Multiple high-performance PLLs allow synthesis of unrelated
frequencies
■ Nonvolatile programming for personalization of PLL
frequencies, spread spectrum characteristics, drive strength,
crystal load capacitance, and output frequencies
■ Application specific programmable EMI reduction using Spread
Spectrum for clocks
■ Programmable PLLs for system frequency margin tests
■ Meets critical timing requirements in complex system designs
■ Suitability for PC, consumer, portable, and networking
applications
■ Capable of Zero PPM frequency synthesis error
■ Uninterrupted system operation during clock frequency switch
■ Application compatibility in standard and low-power systems
Functional Description
For a complete list of related documentation, click here.
OSC PLL1
PLL3
(SS)
CLK3
(SS)
CLK2
(No SS
CLK1
(SS)
Crossbar
Switch
FS1
SSON
XOUT
XIN/
EXCLKIN
PD#/OE
PLL 2
(SS)
FS0
MUX
and
Control
Logic
Output
Dividers
and
Drive
Strength
Control
