Rev 1.0, November 21, 2006 Page 6 of 8
Absolute Maximum Conditions
[2]
Input Voltage Relative to V
SS
:...............................V
SS
– 0.3V
Input Voltage Relative to V
DDQ
or AV
DD
: ........... V
DDQ
+ 0.3V
Storage Temperature: ................................ –65°C to + 150°C
Operating Temperature:.................................... 0°C to +85°C
Maximum Power Supply: ................................................3.5V
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any
voltage higher than the maximum rated voltages to this circuit.
For proper operation, V
in
and V
out
should be constrained to the
range:
V
SS
< (V
in
or V
out
) < V
DDQ
.
Unused inputs must always be tied to an appropriate logic
voltage level (either V
SS
or V
DDQ
).
DC Electrical Specifications (AV
DD
= V
DDQ
= 2.5v ± 5%, T
A
= 0°C to +85°C)
[3]
Parameter Description Condition Min. Typ. Max. Unit
V
DDQ
Supply Voltage Operating 2.38 2.5 2.63 V
V
IL
Input Low Voltage PD# 0.3 × V
DDQ
V
V
IH
Input High Voltage 0.7 × V
DDQ
V
V
ID
Differential Input Voltage
[4]
CLK, FBIN 0.36 V
DDQ
+ 0.3 V
V
IX
Differential Input Crossing Voltage
[5]
CLK, FBIN (V
DDQ
/2) –
0.2
V
DDQ
/2 (V
DDQ
/2) +
0.2
V
I
IN
Input Current [CLK, FBIN, PD#] V
IN
= 0V or V
IN
= V
DDQ
–10 10 µA
I
OL
Output Low Current V
DDQ
= 2.375V, V
OUT
= 1.2V 26 35 mA
I
OH
Output High Current V
DDQ
= 2.375V, V
OUT
= 1V –28 –32 mA
V
OL
Output Low Voltage V
DDQ
= 2.375V, I
OL
= 12 mA 0.6 V
V
OH
Output High Voltage V
DDQ
= 2.375V, I
OH
= –12 mA 1.7 V
V
OUT
Output Voltage Swing
[6]
1.1 V
DDQ
– 0.4 V
V
OC
Output Crossing Voltage
[7]
(V
DDQ
/2) –
0.2
V
DDQ
/2 (V
DDQ
/2) +
0.2
V
I
OZ
High-Impedance Output Current V
O
= GND or V
O
= V
DDQ
–10 10 µA
I
DDQ
Dynamic Supply Current
[8]
All V
DDQ
, F
O
= 170 MHz 235 300 mA
I
DD
PLL Supply Current V
DDA
only 9 12 mA
I
DDS
Standby Supply Current PD# = 0 and CLK/CLK# < 10
MHz
100 µA
Cin Input Pin Capacitance 4 pF
AC Electrical Specifications (AV
DD
= V
DDQ
= 2.5V±5%, T
A
= 0°C to +85°C)
[9, 10]
Parameter Description Condition Min. Typ. Max. Unit
f
CLK
Operating Clock Frequency AV
DD
, V
DDQ
= 2.5V ± 0.2V 60 200 MHz
t
DC
Input Clock Duty Cycle 40 60 %
t
LOCK
Maximum PLL lock Time 100 µs
D
TYC
Duty Cycle
[11]
60 MHz to 100 MHz 49.5 50 50.5 %
101 MHz to 170 MHz 49 51 %
tsl(o) Output Clocks Slew Rate 20%–80% of VOD 1 2 V/ns
Notes:
2. Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
3. Unused inputs must be held HIGH or LOW to prevent them from floating.
4. Differential input signal voltage specifies the differential voltage VTR–VCPI required for switching, where VTR is the true input level and VCP is the complementary
input level. See Figure 6.
5. Differential cross-point input voltage is expected to track V
DDQ
and is the voltage at which the differential signal must be crossing.
6. For load conditions see Figure 6.
7. The value of VOC is expected to be (VTR + VCP)/2. In case of each clock directly terminated by a 120Ω resistor. See Figure 6.
8. All outputs switching load with 14 pF in 60Ω environment. See Figure 6.
9. Parameters are guaranteed by design and characterization. Not 100% tested in production.
10. PLL is capable of meeting the specified parameters while supporting SSC synthesizers with modulation frequency between 30kHz and 50 kHz with a down
spread or –0.5%.
11. While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies. This is due to the formula: duty cycle = t
WHC
/t
C
,
where the cycle time(tC) decreases as the frequency goes up.
