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LT3837IFE#TRPBF

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LT3837
16
3837fd
APPLICATIONS INFORMATION
Setting Feedback Resistive Divider
Use the equation developed in the Operation section for
the feedback divider.
It is recommended that the Thevenin impedance of the
resistors on the FB Pin is roughly 3k for bias current
cancellation and other reasons.
For the example using primary winding sensing if
ESR = 0.002 and R
DS(ON)
= 0.004 then:
R1=
3k
1.237
•
3.3+10• 0.002+0.004
(
( )
1/ 3
( )
– 0.7
= 22.75k
So, choose 22.1k.
Current Sense Resistor Considerations
The external current sense resistor is used to control peak
primary switch current, which controls a number of key
converter characteristics including maximum power and
external component ratings. Use a noninductive current
sense resistor (no wire-wound resistors). Mounting the
resistor directly above an unbroken ground plane con-
nected with wide and short traces keeps stray resistance
and inductance low.
The dual sense pins allow for a fully Kelvined connection.
Make sure that SENSE
+
and SENSE
–
are isolated and con-
nect close to the sense resistor to preserve this.
Peak current occurs at 98mV of sense voltage V
SENSE
. So
the nominal sense resistor is V
SENSE
/I
PK
. For example, a
peak switch current of 10A requires a nominal sense resistor
of 0.010Ω. Note that the instantaneous peak power in the
sense resistor is 1W, and that it is rated accordingly. The
use of parallel resistors can help achieve low resistance,
low parasitic inductance and increased power capability.
Size R
SENSE
using worst-case conditions, minimum L
P
,
V
SENSE
and maximum V
IN
. Continuing the example, let us
assume that our worst-case conditions yield an I
PK
10%
above nominal so I
PK
= 10.41A . If there is a 5% tolerance
on R
SENSE
and minimum V
SENSE
= 80mV, then R
SENSE
•
105% = 88mV/10.41A and nominal R
SENSE
= 8.05mΩ.
Round to the nearest available lower value 8.0mΩ.
Selecting the Load Compensation Resistor
The expression for R
CMP
was derived in the Operation
section for primary winding sensing as:
R
CMP
=K1•
R
SENSE
• 1–DC
( )
ESR+R
DS(ON)
•R1 • N
SP
=R
S(OUT)
Continuing the example:
K1=
V
OUT
V
IN
• Eff
=
3.3
9 88%
( )
= 0.417
If ESR = 0.002Ω and R
DS(ON)
= 0.004Ω
R
CMP
= 0.417 •
8.0mΩ • 1– 0.52
( )
0.002Ω + 0.004Ω
• 22.1kΩ•0.33
=
1.93k
Ω
This value for R
CMP
is a good starting point, but empiri-
cal methods are required for producing the best results.
This is because several of the required input variables are
difficult to estimate precisely. For instance, the ESR term
above includes that of the transformer secondary, but its
effective ESR value depends on high frequency behavior,
not simply DC winding resistance. Similarly, K1 appears
as a simple ratio of V
IN
to V
OUT
times (differential) ef-
ficiency, but theoretically estimating efficiency is not a
simple calculation.
The suggested empirical method is as follows:
1. Build a prototype of the desired supply including the
actual secondary components.
2. Temporarily ground the C
CMP
pin to disable the load
compensation function. Measure output voltage while
sweeping output current over the expected range.
Approximate the voltage variation as a straight line,
∆V
OUT
/∆I
OUT
= R
S(OUT)
.
3. Calculate a value for the K1 constant based on V
IN
, V
OUT
and the measured (differential) efficiency.
4. Compute:
R
CMP
=K1•
R
SENSE
R
S(OUT)
•R1•N
SP
orN
SF
LT3837
17
3837fd
APPLICATIONS INFORMATION
5. Verify this result by connecting a resistor of this value
from the R
CMP
pin to ground.
6. Disconnect the ground short to C
CMP
and connect the
requisite 0.1µF filter capacitor to ground. Measure
the output impedance R
S(OUT)
= ∆V
OUT
/∆I
OUT
with the
new compensation in place. R
S(OUT)
should have
decreased significantly. Fine tuning is accomplished
experimentally by slightly altering R
CMP
. A revised
estimate for R
CMP
is:
′
R
CMP
=R
CMP
• 1+
R
S(OUT)CMP
R
S(OUT)
where R′
CMP
is the new value for the load compensation
resistor, R
S(OUT)CMP
is the output impedance with R
CMP
in place and R
S(OUT)
is the output impedance with no
load compensation (from step 2).
Setting Frequency
The switching frequency of the LT3837 is set by an
external capacitor connected between the OSC pin and
ground. Recommended values are between 200pF and
33pF, yielding switching frequencies between 50kHz and
250kHz. Figure 3 shows the nominal relationship between
external capacitance and switching frequency. Place the
capacitor as close as possible to the IC and minimize OSC
trace length and area to minimize stray capacitance and
potential noise pickup.
You can synchronize the oscillator frequency to an external
frequency. This is done with a signal on the SYNC pin. Set
the LT3837 frequency 10% slower than the desired external
frequency using the OSC pin capacitor, then use a pulse
on the SYNC pin of amplitude greater than 2V and with the
desired period. The rising edge of the SYNC signal initiates
an OSC capacitor discharge forcing primary MOSFET off
(PG voltage goes low). If the oscillator frequency is much
different from the sync frequency, problems may occur
with slope compensation and system stability. Keep the
sync pulse width greater than 500ns.
Selecting Timing Resistors
There are three internal “one-shot” times that are pro-
grammed by external application resistors: minimum
on-time, enable delay time and primary MOSFET turn-on
delay. These are all part of the isolated flyback control
technique, and their functions are previously outlined in
the Theory of Operation section.
The following information should help in selecting and/or
optimizing these timing values.
Minimum On-Time (t
ON(MIN)
)
Minimum on-time is the programmable period during
which current limit is blanked (ignored) after the turn
on of the primary side switch. This improves regulator
performance by eliminating false tripping on the leading
edge spike in the switch, especially at light loads. This
spike is due to both the gate/source charging current and
the discharge of drain capacitance. The isolated flyback
sensing requires a pulse to sense the output. Minimum
on-time ensures that there is always a signal to close the
feedback loop. The LT3837 does not employ cycle skipping
at light loads. Therefore, minimum on-time along with
synchronous rectification sets the switch over in forced
continuous mode operation.
The t
ON(MIN)
resistor is set with the following equation:
R
tON(MIN)
(kΩ)=
t
ON(MIN)
(ns)– 104
1.063
Keep R
tON(MIN)
greater than 70k. A good starting value
is 160k.
Figure 3. f
OSC
vs OSC Capacitor Values
C
OSCAP
(pF)
30
50
f
OSC
(kHz)
100
200
300
100 200
3837 F03
LT3837
18
3837fd
APPLICATIONS INFORMATION
Enable Delay Time (ENDLY)
Enable delay time provides a programmable delay between
turn-off of the primary gate drive node and the subsequent
enabling of the feedback amplifier. As discussed earlier, this
delay allows the feedback amplifier to ignore the leakage
inductance voltage spike on the primary side.
The worst-case leakage spike pulse width is at maximum
load conditions. So set the enable delay time at these
conditions.
While the typical applications for this part use forced
continuous operation, it is conceivable that a secondary-
side controller might cause discontinuous operation at
light loads. Under such conditions the amount of energy
stored in the transformer is small. The flyback waveform
becomes “lazy” and some time elapses before it indicates
the actual secondary output voltage. The enable delay time
should be made long enough to ignore the “irrelevant”
portion of the flyback waveform at light load.
Even though the LT3837 has a robust gate drive, the gate
transition-time slows with very large MOSFETs. Increase
delay time is as required when using such MOSFETs.
The enable delay resistor is set with the following equa-
tion:
R
ENDLY
(kΩ)=
t
ENDLY
(ns)– 30
2.616
Keep R
ENDLY
greater than 40k. A good starting point
is 56k.
Primary Gate Delay Time (PGDLY)
Primary gate delay is the programmable time from the
turn-off of the synchronous MOSFET to the turn-on of
the primary side MOSFET. Correct setting eliminates
overlap between the primary side switch and secondary
side synchronous switch(es) and the subsequent current
spike in the transformer. This spike will cause additional
component stress and a loss in regulator efficiency.
The primary gate delay resistor is set with the following
equation:
R
PGDLY
(kΩ)=
t
PGDLY
(ns)+47
9.01
A good starting point is 27k.
Soft-Start Functions
The LT3837 contains an optional soft-start function that is
enabled by connecting an external capacitor between the
SFST pin and ground. Internal circuitry prevents the control
voltage at the V
C
pin from exceeding that on the SFST pin.
There is an initial pull-up circuit to quickly bring the SFST
voltage to approximately 0.8V. From there it charges to
approximately 2.8V with a 20µA current source.
The SFST node is then discharged to 0.8V when a fault
occurs. A fault is V
CC
too low (undervoltage lockout),
current sense voltage greater than 200mV or the IC’s
thermal (overtemperature) shutdown is tripped. When
SFST discharges, the V
C
node voltage is also pulled low
to below the minimum current voltage. Once discharged,
the SFST recharges up again.
In this manner, switch currents are reduced and the stresses
in the converter are reduced during fault conditions.
The time it takes to fully charge soft-start is:
t
SS
=
C
SFST
• 1.4V
20µA
= 70ms• C
SFST
(µF)
UVLO Pin Function
The UVLO pin provides a user programming undervoltage
lockout. This is usually used to provide undervoltage
lockout based on V
IN
. The gate drivers are disabled when
UVLO is below the 1.24V UVLO threshold. An external
resistive divider between the input supply and ground is
used to set the turn-on voltage.
The bias current on this pin depends on the pin volt-
age and UVLO state. The change provides the user with
adjustable UVLO hysteresis. When the pin rises above
the UVLO threshold a small current is sourced out of the
pin, increasing the voltage on the pin. As the pin voltage
drops below this threshold, the current is stopped, further
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LT3837IFE#TRPBF

Mfr. #:
Buy LT3837IFE#TRPBF
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Isolated No-Opto Synchronous Flyback Controller with Wide Input Voltage
Lifecycle:
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