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NLV74VHCT08DTR2G

P1-P3P4-P6
© Semiconductor Components Industries, LLC, 2015
January, 2015 − Rev. 9
1 Publication Order Number:
MC74VHCT08A/D
MC74VHCT08A
Quad 2-Input AND Gate
The MC74VHCT08A is an advanced high speed CMOS 2−input
AND gate fabricated with silicon gate CMOS technology. It achieves
high speed operation similar to equivalent Bipolar Schottky TTL
while maintaining CMOS low power dissipation.
The VHCT inputs are compatible with TTL levels. This device can
be used as a level converter for interfacing 3.3 V to 5.0 V, because it
has full 5.0 V CMOS level output swings.
The VHCT08A input structures provide protection when voltages
between 0 V and 5.5 V are applied, regardless of the supply voltage.
The output structures also provide protection when V
CC
= 0 V. These
input and output structures help prevent device destruction caused by
supply voltage − input/output voltage mismatch, battery backup, hot
insertion, etc.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V
systems to 3.0 V systems.
Features
• High Speed: t
PD
= 4.3 ns (Typ) at V
CC
= 5 V
• Low Power Dissipation: I
CC
= 2 mA (Max) at T
A
= 25°C
• TTL−Compatible Inputs: V
IL
= 0.8 V; V
IH
= 2.0 V
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
• Designed for 2 V to 5.5 V Operating Range
• Low Noise: V
OLP
= 0.8 V (Max)
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300 mA
• ESD Performance: Human Body Model; > 2000 V,
Machine Model; > 200 V
• Chip Complexity: 24 FETs or 6 Equivalent Gates
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
• These Devices are Pb−Free and are RoHS Compliant
www.onsemi.com
MARKING
DIAGRAMS
TSSOP−14
DT SUFFIX
CASE 948G
1
SOIC−14
D SUFFIX
CASE 751A
1
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
ORDERING INFORMATION
A = Assembly Location
WL, L = Wafer Lot
Y, YY = Year
WW, W = Work Week
G or G = Pb−Free Package
VHCT08AG
AWLYWW
1
14
VHCT
08A
ALYWG
G
1
14
(Note: Microdot may be in either location)
MC74VHCT08A
www.onsemi.com
2
3
Y1
1
A1
Figure 1. Logic Diagram
2
B1
6
Y2
4
A2
5
B2
8
Y3
9
A3
10
B3
11
Y4
12
A4
13
B4
Y = AB
Figure 2. Pinout: 14−Lead Packages
1314 12 11 10 9 8
21 34567
V
CC
B4 A4 Y4 B3 A3 Y3
A1 B1 Y1 A2 B2 Y2 GND
L
L
H
H
L
H
L
H
FUNCTION TABLE
Inputs Output
AB
L
L
L
H
Y
(Top View)
MAXIMUM RATINGS
Rating Symbol Value Unit
DC Supply Voltage V
CC
–0.5 to +7.0 V
DC Input Voltage V
in
–0.5 to +7.0 V
DC Output Voltage V
out
–0.5 to V
CC
+0.5 V
Input Diode Current I
IK
−20 mA
Output Diode Current I
OK
±20 mA
DC Output Current, per Pin I
out
±25 mA
DC Supply Current, V
CC
and GND Pins I
CC
±50 mA
Power Dissipation in Still Air, SOIC Packages†
TSSOP Package†
P
D
500
450
mW
Storage Temperature T
stg
–65 to +150 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of
these limits are exceeded, device functionality should not be assumed, damage may occur and
reliability may be affected.
†Derating − SOIC Packages: – 7 mW/°C from 65° to 125°C
TSSOP Package: − 6.1 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Parameter Symbol Min Max Unit
DC Supply Voltage V
CC
4.5 5.5 V
DC Input Voltage V
in
0 5.5 V
DC Output Voltage V
out
0 V
CC
V
Operating Temperature T
A
−40 + 125 °C
Input Rise and Fall Time V
CC
= 5.0 V ±0.5 V t
r
, t
f
0 20 ns/V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, V
in
and
V
out
should be constrained to the
range GND v (V
in
or V
out
) v V
CC
.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V
CC
).
Unused outputs must be left open.
MC74VHCT08A
www.onsemi.com
3
DC ELECTRICAL CHARACTERISTICS
Parameter Test Conditions
V
CC
(V)
T
A
= 25°C T
A
≤ 85°C T
A
≤ 125°C
Uni
t
Symbol Min Typ Max Min Max Min Max
Minimum High−Level Input Voltage V
IH
3.0
4.5
5.5
1.2
2.0
2.0
1.2
2.0
2.0
1.2
2.0
2.0
V
Maximum Low−Level Input Voltage V
IL
3.0
4.5
5.5
0.53
0.8
0.8
0.53
0.8
0.8
0.53
0.8
0.8
V
Minimum High−Level Output Voltage
V
IN
= V
IH
or V
IL
V
IN
= V
IH
or V
IL
I
OH
= − 50 mA
V
OH
3.0
4.5
2.9
4.4
3.0
4.5
2.9
4.4
2.9
4.4
V
V
IN
= V
IH
or V
IL
I
OH
= −4 mA
I
OH
= −8 mA
3.0
4.5
2.58
3.94
2.48
3.80
2.34
3.66
Maximum Low−Level Output Voltage
V
IN
= V
IH
or V
IL
V
IN
= V
IH
or V
IL
I
OL
= 50 mA
V
OL
3.0
4.5
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
V
V
IN
= V
IH
or V
IL
I
OL
= 4 mA
I
OL
= 8 mA
3.0
4.5
0.36
0.36
0.44
0.44
0.52
0.52
Maximum Input Leakage Current V
IN
= 5.5 V or
GND
I
IN
0 to 5.5 ±0.1 ±1.0 ±1.0
mA
Maximum Quiescent Supply Current V
IN
= V
CC
or GND I
CC
5.5 2.0 20 40
mA
Quiescent Supply Current Input: V
IN
= 3.4 V I
CCT
5.5 1.35 1.50 1.65 mA
Output Leakage Current V
OUT
= 5.5 V I
OPD
0.0 0.5 5.0 10
mA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
AC ELECTRICAL CHARACTERISTICS (Input t
r
= t
f
= 3.0ns)
Characteristic Test Conditions Symbo
l
T
A
= 25°C T
A
≤ 85°C T
A
≤ 125°C
Unit
Min Typ Max Min Max Max Max
Maximum Propagation Delay,
Input A or B to Y
V
CC
= 3.0 ± 0.3V C
L
= 15 pF
C
L
= 50 pF
t
PLH
,
t
PHL
6.2
8.7
8.8
12.3
10.5
14.0
14.0
17.5
ns
V
CC
= 5.0 ± 0.5V C
L
= 15 pF
C
L
= 50 pF
4.3
5.8
5.9
7.9
7.0
9.0
9.0
11.0
Maximum Input Capacitance C
in
4 10 10 10 pF
Power Dissipation Capacitance (Note 1)
C
PD
Typical @ 25°C, V
CC
= 5.0V
20 pF
1. C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: I
CC(OPR
)
= C
PD
V
CC
f
in
+ I
CC
/4 (per gate). C
PD
is used to determine the
no−load dynamic power consumption; P
D
= C
PD
V
CC
2
f
in
+ I
CC
V
CC
.7
NOISE CHARACTERISTICS (Input t
r
= t
f
= 3.0 ns, C
L
= 50pF, V
CC
= 5.0 V)
Characteristic
Symbo
l
T
A
= 25°C
Unit
Typ Max
Quiet Output Maximum Dynamic V
OL
V
OLP
0.3 0.8 V
Quiet Output Minimum Dynamic V
OL
V
OLV
−0.3 −0.8 V
Minimum High Level Dynamic Input Voltage V
IHD
3.5 V
Maximum Low Level Dynamic Input Voltage V
ILD
1.5 V
P1-P3P4-P6

NLV74VHCT08DTR2G

Mfr. #:
Buy NLV74VHCT08DTR2G
Manufacturer:
ON Semiconductor
Description:
Logic Gates 2-INPUT AND GATE
Lifecycle:
New from this manufacturer.
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