Operation modes M48Z08, M48Z18
10/20 Doc ID 2424 Rev 8
Table 4. WRITE mode AC characteristics
2.3 Data retention mode
With valid V
CC
applied, the M48Z08/18 operates as a conventional BYTEWIDE™ static
RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write
protecting itself when V
CC
falls within the V
PFD
(max), V
PFD
(min) window. All outputs
become high impedance, and all inputs are treated as “Don't care.”
Note: A power failure during a WRITE cycle may corrupt data at the currently addressed location,
but does not jeopardize the rest of the RAM's content. At voltages below V
PFD
(min), the
user can be assured the memory will be in a write protected state, provided the V
CC
fall time
is not less than t
F
. The M48Z08/18 may respond to transient noise spikes on V
CC
that reach
into the deselect window during the time the device is sampling V
CC
. Therefore, decoupling
of the power supply lines is recommended.
When V
CC
drops below V
SO
, the control circuit switches power to the internal battery which
preserves data. The internal button cell will maintain data in the M48Z08/18 for an
accumulated period of at least 11 years when V
CC
is less than V
SO
.
As system power returns and V
CC
rises above V
SO
, the battery is disconnected, and the
power supply is switched to external V
CC
. Write protection continues until V
CC
reaches V
PFD
(min) plus t
rec
(min). E should be kept high as V
CC
rises past V
PFD
(min) to prevent
inadvertent write cycles prior to system stabilization. Normal RAM operation can resume t
rec
after V
CC
exceeds V
PFD
(max). For more information on battery storage life refer to the
application note AN1012.
Symbol Parameter
(1)
1. Valid for ambient operating temperature: T
A
= 0 to 70 °C; V
CC
= 4.75 to 5.5 V or 4.5 to 5.5 V (except where
noted).
M48Z08/M48Z18
Unit
Min Max
t
AVAV
WRITE cycle time 100 ns
t
AVWL
Address valid to WRITE enable low 0 ns
t
AVEL
Address valid to chip enable 1 low 0 ns
t
WLWH
WRITE enable pulse width 80 ns
t
ELEH
Chip enable low to chip enable 1 high 80 ns
t
WHAX
WRITE enable high to address transition 10 ns
t
EHAX
Chip enable high to address transition 10 ns
t
DVWH
Input valid to WRITE enable high 50 ns
t
DVEH
Input valid to chip enable 1 high 30 ns
t
WHDX
WRITE enable high to input transition 5 ns
t
EHDX
Chip enable high to input transition 5 ns
t
WLQZ
(2)(3)
2. C
L
= 30 pF.
3. If E
goes low simultaneously with W going low, the outputs remain in the high impedance state.
WRITE enable low to output Hi-Z 50 ns
t
AVWH
Address valid to WRITE enable high 80 ns
t
AVEH
Address valid to chip enable high 80 ns
t
WHQX
(2)(3)
WRITE enable high to output transition 10 ns
