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AS7C34096A-12JCNTR

P1-P3P4-P6P7-P9
®
AS7C34096A
8/17/04, v. 2.1 Alliance Semiconductor P. 4 of 9
Key to switching waveforms
Read waveform 1 (address controlled)
3,6,7,9
Read waveform 2 (CE
, OE controlled)
3,6,8,9
Read cycle (over the operating range)
3,9
Parameter Symbol
–10 –12 –15 –20
Unit NotesMin Max Min Max Min Max Min Max
Read cycle time
t
RC
10–12–15–20–ns
Address access time
t
AA
–10–12–15–20ns3
Chip enable (CE
) access time
t
ACE
–10–12–15–20ns3
Output enable (OE
) access time
t
OE
–4–5–6–7ns
Output hold from address change
t
OH
3–3–3–3–ns5
CE
Low to output in low Z
t
CLZ
3–3–3–3–ns4, 5
CE
High to output in high Z
t
CHZ
–5–6–7–9ns4, 5
OE
Low to output in low Z
t
OLZ
0–0–0–0–ns4, 5
OE
High to output in high Z
t
OHZ
–5–6–7–9ns4, 5
Power up time
t
PU
0–0–0–0–ns4, 5
Power down time
t
PD
–10–12–15–20ns4, 5
Undefined/don’t careFalling inputRising input
Address
D
OUT
Data valid
t
OH
t
AA
t
RC
current
Supply
OE
D
OUT
t
OE
t
OLZ
t
ACE
t
CHZ
t
CLZ
t
PU
t
PD
I
CC
I
SB
50% 50%
t
OHZ
Data valid
t
RC1
CE
®
AS7C34096A
8/17/04, v. 2.1 Alliance Semiconductor P. 5 of 9
Write waveform 1 (WE controlled)
10
Write cycle (over the operating range)
10
Parameter Symbol
–10 –12 –15 –20
Unit NotesMin Max Min Max Min Max Min Max
Write cycle time
t
WC
10–12–15–20–ns
Chip enable (CE
) to write end
t
CW
7 – 8 –10–12–ns
Address setup to write end
t
AW
7 – 8 –10–12–ns
Address setup time
t
AS
0–0–0–0–ns
Write pulse width (OE
= high)
t
WP1
7 – 8 –10–12–ns
Write pulse width (OE
= low
t
WP2
10–12–15–20–ns
Address hold from end of write
t
AH
0–0–0–0–ns
Write recovery time
t
WR
0–0–0–0–ns
Data valid to write end
t
DW
5–6–7–9–ns
Data hold time
t
DH
0–0–0–0–ns4, 5
Write enable to output in high Z
t
WZ
05060709ns4, 5
Output active from write end
t
OW
3–3–3–3–ns4, 5
t
AW
t
AH
t
WC
Address
WE
D
OUT
t
DH
t
OW
t
DW
t
WZ
t
WP
t
AS
Data valid
D
IN
t
WR
®
AS7C34096A
8/17/04, v. 2.1 Alliance Semiconductor P. 6 of 9
Write waveform 2 (CE controlled)
10
AC test conditions
Notes
1During V
CC
power-up, a pull-up resistor to V
CC
on CE is required to meet I
SB
specification.
2 This parameter is sampled, but not 100% tested.
3 For test conditions, see AC Test Conditions.
4t
CLZ
and t
CHZ
are specified with C
L
= 5pF as in Figure B. Transition is measured ±500 mV from steady-state voltage.
5 This parameter is guaranteed, but not tested.
6WE
is HIGH for read cycle.
7CE
and OE are LOW for read cycle.
8 Address valid prior to or coincident with CE
transition Low.
9 All read cycle timings are referenced from the last valid address to the first transitioning address.
10 All write cycle timings are referenced from the last valid address to the first transitioning address.
11 C=30pF, except on High Z and Low Z parameters, where C=5pF.
t
AW
Address
CE
WE
D
OUT
t
CW
t
WP
t
DW
t
DH
t
AH
t
WZ
t
WC
t
AS
Data valid
D
IN
t
WR
350
Ω
C
11
320
Ω
D
OUT
GND
+3.3V
Figure B: 3.3V Output load
- Output load: see Figure B.
- Input pulse level: GND to 3.0V. See Figures A and B.
- Input rise and fall times: 2 ns. See Figure A.
- Input and output timing reference levels: 1.5V.
168
Ω
Thevenin equivalent:
D
OUT
+1.728V
10%
90%
10%
90%
GND
+3.0V
Figure A: Input pulse
2 ns
P1-P3P4-P6P7-P9

AS7C34096A-12JCNTR

Mfr. #:
Buy AS7C34096A-12JCNTR
Manufacturer:
Alliance Memory
Description:
SRAM 4M, 3.3V, 12ns, FAST 512K x 8 Asynch SRAM
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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