10
Figure 3. Recommended Gigabit/sec Ethernet HFBR-5912EZ Fiber-Optic Transceiver and HDMP-1636A/1646A
SERDES Integrated Circuit Transceiver Interface and Power Supply Filter Circuits.
50
7
9
10
6
2
3
4
1
OUTPUT
DRIVER
LASER
DRIVER
CIRCUIT
PRE-
AMPLIFIER
TO LVTTL STAGE
5
3.3 V dc
L1
1 µH
C5*
0.01 µF
C11
0.1 µF
R7*
3.3 k
3.3 V dc
50
+
+
3.3 V dc
GND
TD+
TD-
RD-
RD+
TD+
TD-
RD-
RD+
S
D
V
CCR
V
CCT
V
EET
V
E
E
R
HFBR-5912EZ
FIBER-OPTIC
TRANSCEIVER
NOTES:
USE SURFACE-MOUNT COMPONENTS FOR OPTIMUM HIGH-FREQUENCY PERFORMANCE.
USE 50Ω MICROSTRIP OR STRIPLINE FOR SIGNAL PATHS.
LOCATE 50Ω TERMINATIONS AT THE INPUTS OF RECEIVING UNITS.
* IN ORDER TO ELIMINATE REQUIRED EXTERNAL PASSIVE COMPONENTS, AVAGO TECHNOLOGIES HAS INCLUDED THE EQUIVALENT OF RESISTORS R5 - R8 AND
CAPACITORS C5 AND C6 WITHIN THE MODULE. R5 - R8, C5 AND C6 ARE INCLUDED AS PART OF THE APPLICATION CIRCUIT TO ACCOMMODATE OTHER TRANSCEIVER
VENDORS' MODULES. THE HFBR-5912EZ WILL OPERATE IN BOTH CONFIGURATIONS.
**C8 IS A RECOMMENDED BYPASS CAPACITOR FOR ADDITIONAL LOW FREQUENCY NOISE FILTERING.
THE SIGNAL DETECT OUTPUT ON THE HFBR-5912EZ CONTAINS AN INTERNAL 1.8 k PULL UP RESISTOR.
V
CC
2V
EE
2
SEE HDMP-1636A/-1646A DATA SHEET FOR
DETAILS ABOUT THIS TRANSCEIVER IC.
PECL
INPUT
POST-
AMPLIFIER
SIGNAL
DETECT
CIRCUIT
R8*
3.3 k
CLOCK
SYNTHESIS
CIRCUIT
PARALLEL
TO SERIAL
CIRCUIT
R5*
5.1 k
R6*
5.1 k
R10
150
R9
150
L2
1 µH
HDMP-1636A/-1646A
SERIAL/DE-SERIALIZER
(SERDES - 10 BIT
TRANSCEIVER)
C1
0.1 µF
C2
0.1 µF
50
R14
100
50
CLOCK
RECOVERY
CIRCUIT
SERIAL TO
PARALLEL
CIRCUIT
INPUT
BUFFER
R3
130
R4
130
100
C8**
10 µF
C6*
0.01 µF
C7
0.1 µF
C10
10 µF
C3
0.01 µF
C4
0.01 µF
C9
0.1 µF
8
TRANSMIT
DISABLE
V
CC
TO
LVTTL
STAGE
1.8
k
