24
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V51433/72V51443/72V51453 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(16 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
PAFn FLAG BUS OPERATION
The IDT72V51433/72V51443/72V51453 multi-queue flow-control devices
can be configured for up to 16 queues, each queue having its own almost full
status. An active queue has its flag status output to the discrete flags, FF and PAF,
on the write port. Queues that are not selected for a write operation can have
their PAF status monitored via the PAFn bus. The PAFn flag bus is 8 bits wide,
so that 8 queues at a time can have their status output to the bus. If 9 or more
queues are setup within a device then there are 2 methods by which the device
can share the bus between queues, "Direct" mode and "Polled" mode
depending on the state of the FM (Flag Mode) input during a Master Reset. If
8 or less queues are setup within a device then each will have its own dedicated
output from the bus. If 8 or less queues are setup in single device mode, it is
recommended to configure the PAFn bus to polled mode as it does not require
using the write address (WRADD).
PAFn - DIRECT BUS
If FM is LOW at master reset then the PAFn bus operates in Direct (addressed)
mode. In direct mode the user can address the sector of queues they require
to be placed on to the PAFn bus. For example, consider the operation of the
PAFn bus when 10 queues have been setup. To output status of the first sector,
Queue[0:7] the WRADD bus is used in conjunction with the FSTR (PAF flag
strobe) input and WCLK. The address present on the significant bit of the
WRADD bus with FSTR HIGH will be selected as the sector address on a rising
edge of WCLK. So to address sector 1, Queue[0:7] the WRADD bus should be
loaded with “xxxxxx0”, the PAFn bus will change status to show the new sector
selected 1 WCLK cycle after sector selection. PAFn[0:7] gets status of queues,
Queue[0:7] respectively.
To address the second sector, Queue[8:15], the WRADD address is
“xxxxxx1”. PAF[0:1] gets status of queues, Queue[9:10] respectively. Remem-
ber, only 10 queues were setup, so when sector 2 is selected the unused outputs
PAF[2:7] will be don't care states.
Note, that if a read or write operation is occurring to a specific queue, say
queue ‘x’ on the same cycle as a sector switch which will include the queue ‘x’,
then there may be an extra WCLK cycle delay before that queues status is
correctly shown on the respective output of the PAFn bus. However, the active
PAF flag will show correct status at all times.
Sectors can be selected on consecutive clock cycles, that is the sector on the
PAFn bus can change every WCLK cycle. Also, data present on the input bus,
Din, can be written into a queue on the same WCLK rising edge that a sector
is being selected, the only restriction being that a write queue selection and PAFn
sector selection cannot be made on the same cycle.
If 8 or less queues are setup then queues, Queue[0:7] have their PAF status
output on PAF[0:7] constantly.
When the multi-queue devices are connected in expansion of more than one
device the PAFn busses of all devices are connected together, when switching
between sectors of different devices the user must utilize the 3 most significant
bits of the WRADD address bus (as well as the 2 LSB’s). These 3 MSB’s
correspond to the device ID inputs, which are the static inputs, ID0, ID1 & ID2.
Please refer to Figure 23
PAF
n - Direct Mode Sector Selection for timing
information. Also refer to Table 1, Write Address Bus, WRADD.
PAFn – POLLED BUS
If FM is HIGH at master reset then the PAFn bus operates in Polled (looped)
mode. In polled mode the PAFn bus automatically cycles through the 2 sectors
within the device regardless of how many queues have been setup in the part.
Every rising edge of the WCLK causes the next sector to be loaded on the PAFn
bus. The device configured as the master (MAST input tied HIGH), will take
control of the PAFn after MRS goes LOW. For the whole WCLK cycle that the
first sector is on PAFn the FSYNC (PAFn bus sync) output will be HIGH, for the
2nd sector, this FSYNC output will be LOW. This FSYNC output provides the
user with a mark with which they can synchronize to the PAFn bus, FSYNC is
always HIGH for the WCLK cycle that the first sector of a device is present on
the PAFn bus.
When devices are connected in expansion mode, only one device will be
set as the Master, MAST input tied HIGH, all other devices will have MAST tied
LOW. The master device is the first device to take control of the PAFn bus and
will place its first sector on the bus on the rising edge of WCLK after the MRS
input goes HIGH. For the next 3 WCLK cycles the master device will maintain
control of the PAFn bus and cycle its sectors through it, all other devices hold
their PAFn outputs in High-Impedance. When the master device has cycled its
sectors it passes a token to the next device in the chain and that device assumes
control of the PAFn bus and then cycles its sectors and so on, the PAFn bus
control token being passed on from device to device. This token passing is done
via the FXO outputs and FXI inputs of the devices (“PAF Expansion Out” and
“PAF Expansion In”). The FXO output of the master device connects to the FXI
of the second device in the chain and the FXO of the second connects to the FXI
of the third and so on. The final device in a chain has its FXO connected to the
FXI of the first device, so that once the PAFn bus has cycled through all sectors
of all devices, control of the PAFn will pass to the master device again and so
on. The FSYNC of each respective device will operate independently and
simply indicate when that respective device has taken control of the bus and is
placing its first sector on to the PAFn bus.
When operating in single device mode the FXI input must be connected to
the FXO output of the same device. In single device mode a token is still required
to be passed into the device for accessing the PAFn bus.
Please refer to Figure 26,
PAF
n Bus – Polled Mode for timing information.
PAEn FLAG BUS OPERATION
The IDT72V51433/72V51443/72V51453 multi-queue flow-control devices
can be configured for up to 16 queues, each queue having its own almost empty
status. An active queue has its flag status output to the discrete flags, OV and PAE,
on the read port. Queues that are not selected for a read operation can have
their PAE status monitored via the PAEn bus. The PAEn flag bus is 8 bits wide,
so that 8 queues at a time can have their status output to the bus. If 9 or more
queues are setup within a device then there are 2 methods by which the device
can share the bus between queues, "Direct" mode and "Polled" mode
depending on the state of the FM (Flag Mode) input during a Master Reset. If
8 or less queues are setup within a device then each will have its own dedicated
output from the bus. If 8 or less queues are setup in single device mode, it is
recommended to configure the PAFn bus to polled mode as it does not require
using the write address (WRADD).
PAEn - DIRECT BUS
If FM is LOW at master reset then the PAEn bus operates in Direct (addressed)
mode. In direct mode the user can address the sector of queues they require
to be placed on to the PAEn bus. For example, consider the operation of the
PAEn bus when 10 queues have been setup. To output status of the first sector,
Queue[0:7] the RDADD bus is used in conjunction with the ESTR (PAE flag
strobe) input and RCLK. The address present on the least significant bit of the
RDADD bus with ESTR HIGH will be selected as the sector address on a rising
edge of RCLK. So to address sector 1, Queue[0:7] the RDADD bus should be
loaded with “xxxxxx0”, the PAEn bus will change status to show the new sector
selected 1 RCLK cycle after sector selection. PAEn[0:7] gets status of queues,
Queue[0:7] respectively.
To address the 2nd sector, Queue[8:15], the RDADD address is “xxxxxx1”.
PAE[0:1] gets status of queues, Queue[9:10] respectively. Remember, only 10
