13
LTC1412
APPLICATIONS INFORMATION
WUU
U
plane to the power supply should be low impedance.
Digital circuitry grounds must be connected to the digital
supply common. Low impedance analog and digital power
supply lines are essential to low noise operation of the
ADC. The traces connecting the pins and bypass capaci-
tors must be kept short and should be made as wide as
possible.
The LTC1412 has differential inputs to minimize noise
coupling. Common mode noise on the A
IN
+
and A
IN
leads
will be rejected by the input CMRR. The A
IN
input can be
used as a ground sense for the A
IN
+
input; the LTC1412
will hold and convert the difference voltage between A
IN
+
and A
IN
. The leads to A
IN
+
(Pin 1) and A
IN
(Pin 2) should
be kept as short as possible. In applications where this is
not possible, the A
IN
+
and A
IN
traces should be run side
by side to equalize coupling.
Supply Bypassing
High quality, low series resistance ceramic, 10µF bypass
capacitors should be used at the V
DD
and REFCOMP pins.
Surface mount ceramic capacitors such as Murata
GRM235Y5V106Z016 provide excellent bypassing in a
small board space. Alternatively 10µF tantalum capacitors
in parallel with 0.1µF ceramic capacitors can be used.
Bypass capacitors must be located as close to the pins as
possible. The traces connecting the pins and the bypass
capacitors must be kept short and should be made as wide
as possible.
Example Layout
Figures 13a, 13b, 13c and 13d show the schematic and
layout of an evaluation board. The layout demonstrates the
proper use of decoupling capacitors and ground plane
with a two layer printed circuit board.
Figure 12. Power Supply Grounding Practice
LTC1412
A
IN
+
ANALOG INPUT
A
IN
V
REF
REFCOMP
AGND
1412 F11b
1
2
3
R4
100
R2
50k
R3
24k
–5V
R6
24k
R1
50k
R5
47k
4
5
10µF
Figure 11b. Offset and Full-Scale Adjust Circuit
0.61mV (i.e., –0.5LSB) at A
IN
+
and adjust the offset at
the A
IN
input until the output code flickers between 0000
0000 0000 and 1111 1111 1111. For full-scale adjust-
ment, an input voltage of 2.49817V (FS/2 – 1.5LSBs) is
applied to A
IN
+
and R2 is adjusted until the output code
flickers between 0111 1111 1110 and 0111 1111 1111.
Board Layout and Bypassing
To obtain the best performance from the LTC1412, a
printed circuit board with ground plane is required. Layout
for the printed circuit board should ensure that digital and
analog signal lines are separated as much as possible. In
particular, care should be taken not to run any digital line
alongside an analog signal line.
An analog ground plane separate from the logic system
ground should be established under and around the ADC.
Pin 5 (AGND), Pins 19 and 14 (DGND) and Pin 22 (OGND)
and all other analog grounds should be connected to this
single analog ground point. The REFCOMP bypass capaci-
tor and the DV
DD
bypass capacitor should also be con-
nected to this analog ground plane, see Figure 12. All
analog circuitry grounds should be terminated to this
analog ground plane. The ground return from the ground
1412 F12
A
IN
+
AGNDREFCOMP V
SS
AV
DD
LTC1412
DIGITAL
SYSTEM
ANALOG
INPUT
CIRCUITRY
54
2
26
OV
DD
DV
DD
21 20, 2728
OGND
DGND
14, 19 22
POWER
SUPPLY
GROUND
1
0.1µF
A
IN
0.1µF0.1µF
10µF
ANALOG GROUND PLANE
+
+
10µF10µF
++
14
LTC1412
APPLICATIONS INFORMATION
WUU
U
OV
DD
OV
DD
+
E3
7V TO
15V
E2
GND
E4
OPTIONAL
A
+
A
V
CC
V
CC
V
SS
JP7
U1
LTC1412
B[00:11]
U6
74HC574
U7
74HC574
56
U5F
74HC14
U5C
74HC14
9 8 RDY
U5D
74HC14
D11
D1
D3
D5
D7
D9
D11
D10
D8
D6
D4
D2
D0
D11
JP1
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D[0:11]
R1, 1.2k
R2, 1.2k
R3, 1.2k
R4, 1.2k
R5, 1.2k
R6, 1.2k
R7, 1.2k
R9, 1.2k
R8, 1.2k
R10, 1.2k
R11, 1.2k
R12, 1.2k
11 10
U5E
74HC14
R13
1k
1213
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D10
D9
D8
D7
D6
D5
D4
D0
D1
D2
D3
D11
19
18
17
16
15
14
13
12
19
18
17
16
15
14
13
12
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
0E
0E
NOTES: UNLESS OTHERWISE SPECIFIED
1. ALL RESISTOR VALUES 1/8W, 5% SMT
2. ALL CAPACITOR VALUES 50V, 20% SMT
V
SS
V
CC
CLK
J3
V
IN
U2
LT1121-5
U4
LT1175
D13
SS12
R17
10k
R18
10k
R19
51
R16
51
R15
51
U5A
74HC14
JP8
U5B
74HC14
C6
470pF
C10
1µF
16V
C11
10µF
16V
C13
0.1µF
C20
15pF
C14
0.1µF
C1
22µF
10V
TAB GND
1
42
3
C2
0.1µF
C9
0.1µF
U3
LT1363
3
2
1
23
4
6
7
1
8
5
4
J1
J2
JP6
V
OUT
1
2
3
4
5
14
23
24
25
20
19
26
27
28
6
7
8
9
10
11
12
13
15
16
17
18
22
21
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
B0
B1
B2
B3
B11
B10
B9
B8
B7
B6
B5
B4
1
11
2
3
4
5
6
7
8
9
1
11
2
3
4
5
6
7
8
9
D11 (MSB)
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
OGND
OV
DD
+A
IN
–A
IN
V
REF
REFCOMP
AGND
DGND
CONVST
CS
BUSY
DV
DD
DGND
V
SS
DV
DD
AV
DD
JP5
V
CC
3.3V
3.3V
+
OV
DD
C5
10µF
10V
C4
0.1µF
+
1412 F13a
JP2
HEADER
1
3
5
7
9
11
13
15
2
4
6
8
10
12
14
16
C8
0.1µF
OV
DD
C7
0.1µF
GND
GND
12
+
C3
0.1µF
JP3
JP4
R14
20
SHDN
INPUT
INPUT
LIM2
SENSE
OUT
LIM4
GND
1
8
4
3
27
65
E1
7V TO
15V
D14
SS12
+
C12
22µF
10V
V
SS
OV
DD
C19
0.1µF
U5
DECOUPLING
CLK
CLK
20
10
20
10
21
21
12
12
2
1
Figure 13a. LTC1412 Demonstration Board Features Analog Input Signal Buffer, 3Msps, Parallel Data Output 12-Bit ADC,
Data Latches and LED Binary Data Display. Latched Conversion Data is Available on the 16-Pin Header, P2
15
LTC1412
APPLICATIONS INFORMATION
WUU
U
Figure 13b. Component Side Silkscreen
Figure 13c. Component Side
Figure 13d. Solder Side
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

LTC1412IG#TRPBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 12-B, 3Msps, Smpl A/D Conv
Lifecycle:
New from this manufacturer.
Delivery:
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