CA5420AMZ96

CA5420A
7
FN1925.9
February 11, 2015
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FIGURE 6. OUTPUT VOLTAGE vs LOAD SINKING CURRENT FIGURE 7. SUPPLY CURRENT vs OUTPUT VOLTAGE
FIGURE 8. OUTPUT VOLTAGE SWING vs LOAD RESISTANCE FIGURE 9. INPUT BIAS CURRENT DRIFT (I
B
/T)
FIGURE 10. INPUT NOISE VOLTAGE vs FREQUENCY FIGURE 11. OPEN LOOP GAIN AND PHASE SHIFT RESPONSE
Typical Performance Curves (Continued)
V- = -2V
V- = -5V
V- = -10V
V- = -20V
V+ = 0V
T
A
= +25°C
1010.10.01
LOAD (SINKING) CURRENT (mA)
10
100
1000
OUTPUT STAGE TRANSISTOR SATURATION
VOLTAGE, Q17 (mV)
2400
2000
1600
1200
800
400
01 2345
OUTPUT VOLTAGE (V)
SUPPLY CURRENT (µA)
V+ = 5V
V- = GND
5.00
3.75
2.50
1.25
0
0 1 10 100 1k
LOAD RESISTANCE (kΩ)
OUTPUT VOLTAGE SWING (V)
V+ = 5V
T
A
= +25°C
V- = GND
R
L
TO GND
800
700
600
500
400
300
200
100
0
25 35 45 55 65 75 85 95 105 115 125
TEMPERATURE (°C)
INPUT BIAS CURRENT (pA)
V+ = 5V
V- = GND
V
S
= ±10V
V
S
= ±5V
V
S
= ±1V
10
6
FREQUENCY (Hz)
10
5
10
4
10
3
10
2
10
1
1
10
1
100
1000
T
A
= +25°C
EQUIVALENT INPUT NOISE VOLTAGE (nV√Hz)
FREQUENCY (Hz)
10
6
10
5
10
4
10
2
10
1
110
3
V+ = +10V, V- = 10V
T
A
=+ 25°C
R
L
= 10kΩ
C
L
= 0pF
0
20
40
60
80
100
-180
-135
-90
-45
0
OPEN LOOP VOLTAGE GAIN (dB)
OPEN LOOP PHASE (°)
CA5420A
8
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in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN1925.9
February 11, 2015
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About Intersil
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address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
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Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision.
DATE REVISION CHANGE
February 11, 2015 FN1925.9 Electrical Specifications Table: On page 3, Large signal voltage gain Vo = 0.7 to 3V Min limit changed from 80
to 70, and page 4 Large signal voltage gain Vo = 0.7 to 2.5V Min limit changed from 75 to 70.
September 25, 2013 FN1925.8 Page 5 - Changed CMRR limits for ±1V spec table from 60dB to 50dB
Page 9 -
Updated POD to rev 4. Changes from rev 3: Changed Note 1 "1982" to "1994".
July 8, 2011 FN1925.7 page 1 Features: Change "2V Supply at 300µA....." to "2V Supply at 350µA....."
page 3 Updated Thermal Resistance note for package.
page 3 Electrical Spec Table, V+ = 5V, V- = 0V (lower table): change PSRR min from 75dB to 70dB.
page 4 Electrical Spec Table, V+ = 5V, V- = 0V (upper table) Change Supply Current Vo =0V Max from 500µA to
550µA, and V0 = 2.5V change max from 550µA to 600µA.
page 4 Electrical Spec Table, TA = -55 to +125 V+ = 5V, V- = 0V (lower table) change Supply Current VO=0V Max
from 550µA to 600µA, change Vo=2.5V max from 600uA to 650uA.
page 5 Electrical Spec Table Vsupply =+/-1V (upper table) Common Mode Rejection Ratio, delete 1000uV/V
MAX spec and leave only a typ spec. PSRR change 320uV/V max to 425µV/V max.
page 9 POD M8.15 Updated to new POD format by removing table and moving dimensions onto drawing and
adding land pattern. Changed in Typical Recommended Land Pattern the following:
2.41(0.095) to 2.20(0.087)
0.76 (0.030) to 0.60(0.023)
0.200 to 5.20(0.205)
December 08, 2009 FN1925.6 Electrical Specifications Table; TA = 25°C, V+ = 5V, V- = 0V; Change Input Offset Current Max from 0.5pA to 4pA
P3, same table as above; Input Current Max from 1pA to 5pA.
P4: same table as above; Output Voltage VOM+: Minimum spec for RL = Infinity from 4.9V to 4.85V
P5: In Vsupply = +/-1V, Large Signal Voltage Gain spec : Min from 20kV/V to 10kV/V and from 86dB to 80dB
P4; Large Signal Voltage Gain RL = inf; change min to 65dB and typ to75dB (was 85dB Min and 87dB Typ)
Updated Pb-free bullet in Features and Pb-free note in Ordering Information per Mark Kwoka's new verbiage
based on lead finish. Added TB347 link to ordering information for reel specifications. Added MSL link to Order
Info
Updated Caution statement in Abs Max per legal's new verbiage.
Added Pb-Free Reflow link to Thermal Info
Added POD to last page
Added standard Over Temp note to applicable elec spec tables
Corrected Input Offset Current Max from 0.4pA to 4pA
December 21, 2005 FN1925.5 Added redline release FGs to ordering information table.
September 1998 FN1925.4 Initial Release
CA5420A
9
FN1925.9
February 11, 2015
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Package Outline Drawing
M8.15
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 4, 1/12
DETAIL "A"
TOP VIEW
INDEX
AREA
123
-C-
SEATING PLANE
x 45°
NOTES:
1. Dimensioning and tolerancing per ANSI Y14.5M-1994.
2. Package length does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
3. Package width does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
4. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
5. Terminal numbers are shown for reference only.
6. The lead width as measured 0.36mm (0.014 inch) or greater above the
seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch).
7. Controlling dimension: MILLIMETER. Converted inch dimensions are not
necessarily exact.
8. This outline conforms to JEDEC publication MS-012-AA ISSUE C.
SIDE VIEW “A
SIDE VIEW “B”
1.27 (0.050)
6.20 (0.244)
5.80 (0.228)
4.00 (0.157)
3.80 (0.150)
0.50 (0.20)
0.25 (0.01)
5.00 (0.197)
4.80 (0.189)
1.75 (0.069)
1.35 (0.053)
0.25(0.010)
0.10(0.004)
0.51(0.020)
0.33(0.013)
0.25 (0.010)
0.19 (0.008)
1.27 (0.050)
0.40 (0.016)
1.27 (0.050)
5.20(0.205)
1
2
3
4
5
6
7
8
TYPICAL RECOMMENDED LAND PATTERN
2.20 (0.087)
0.60 (0.023)

CA5420AMZ96

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Operational Amplifiers - Op Amps W/ANNEAL OPAMP 1 5MHZ LWBIAS 0 001NA
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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