SY88983VMG

4
SY88983V
Micrel, Inc.
M9999-020205
hbwhelp@micrel.com or (408) 955-1690
February 2005
V
CC
= 3.0V to 3.6V or 4.5V to 5.5V; R
LOAD
= 50 to V
CC
; T
A
= 40°C to +85°C; typical values at V
CC
= 3.3V, T
A
= 25°C.
Symbol Parameter Condition Min Typ Max Units
HYS SD Hysteresis Note 7 2 4.6 8 dB
PSRR Power Supply Rejection Ratio 35 dB
t
OFF
SD Release Time 0.1 0.5 µs
t
ON
SD Assert Time 0.2 0.5 µs
t
r
, t
f
Differential Output Rise/Fall Time 60 120 ps
(20% to 80%) Note 8
t
JITTER
Deterministic Note 9 15 ps
p-p
Random 5ps
rms
V
ID
Differential Input Voltage Swing 10 1800 mV
p-p
V
OD
Differential Output Voltage Swing Note 10 550 800 mV
p-p
V
SR
SD Sensitivity Range Note 11 10 50 mV
p-p
A
V(Diff)
Differential Voltage Gain 32 38 dB
B
3dB
3dB Bandwidth 2.2 GHz
S
21
Single-Ended Small Signal-Gain 26 32 dB
Notes:
7. Electrical signal.
8. With input signal V
ID
> 50mV
p-p
and 50 load.
9. Deterministic jitter measured using K28.5 pattern at 2.488Gbps, V
ID
= 10mV
p-p
. Random jitter measured using K28.7 pattern at 2.488Gbps, V
ID
=
10mV
p-p
.
10. Input is a 200MHz square wave, t
r
< 300ps, 50 load. V
ID
14mV
p-p
.
11. This is the detectable range of input amplitudes that can de-assert SD. The input amplitude to assert SD is 28dB higher than the de-assert
amplitude. See
Typical Operating Characteristics
for a graph showing how to choose a particular R
SDLVL
for a particular SD de-assert, and its
associated assert, amplitude.
AC ELECTRICAL CHARACTERISTICS
TYPICAL OPERATING CHARACTERISTICS
0
10
20
30
40
50
60
70
80
90
10 100 1000 10000 100000
V
ID
(mV
P-P
)
R
SDLVL
SD Assert/Deassert Level
vs. R
SDLVL
ASSERT
DEASSERT
V
CC
= 3.3V, GND = 0V, T
A
= 25°C unless otherwise stated.
5
SY88983V
Micrel, Inc.
M9999-020205
hbwhelp@micrel.com or (408) 955-1690
February 2005
DETAILED DESCRIPTION
The SY88983V low power limiting post amplifier operates
from a single +3.3V or +5V power supply, over temperatures
from 40°C to +85°C. Signals with data rates up to 3.2Gbps
and as small as 10mV
p-p
can be amplified. Figure 1 shows
the allowed input voltage swing. The SY88983V generates
an SD output, allowing feedback to EN for output stability.
SD
LVL
sets the sensitivity of the input amplitude detection.
Input Amplifier/Buffer
The SY88983Vs inputs are internally terminated with 50
to V
REF
. Unless they are not affected by this internal
termination scheme, upstream devices need to be
AC-coupled to the SY88983Vs inputs. Figure 2 shows a
simplified schematic of the input stage.
The high sensitivity of the input amplifier allows signals
as small as 10mV
p-p
to be detected and amplified. The
input amplifier allows input signals as large as 1800mV
p-p
.
Input signals are linearly amplified with a typically 38dB
differential voltage gain. Since it is a limiting amplifier, the
SY88983V outputs typically 800mV
p-p
voltage-limited
waveforms for input signals that are greater than 10mV
p-p
.
Applications requiring the SY88983V to operate with high-
gain should have the upstream TIA placed as close as
possible to the SY88983Vs input pins to ensure the best
performance of the device.
Output Buffer
The SY88983Vs CML output buffer is designed to drive
50 lines. The output buffer requires appropriate termination
for proper operation. An external 50 resistor to V
CC
or
equivalent for each output pin provides this. Figure 3 shows
a simplified schematic of the output stage and includes an
appropriate termination method. Of course, driving a
downstream device with a CML input that is internally
terminated with 50 to V
CC
eliminates the need for external
termination. As noted in the previous section, the amplifier
outputs typically 800mV
p-p
waveforms across 25 total
loads. The output buffer, thus, switches typically 16mA tail-
current. Figure 4 shows the power supply current
measurement, which excludes the 16mA tail-current.
Signal Detect
The SY88983V generates a chatter-free signal detect
(SD) open-collector TTL output with internal 5k pull-up
resistor as shown in Figure 5. SD is used to determine that
the input amplitude is large enough to be considered a
valid input. SD asserts high if the input amplitude rises
above the threshold set by SD
LVL
and de-asserts low
otherwise. SD can be fed back to the enable (EN) input to
maintain output stability under a loss-of-signal condition.
EN de-asserts low the true output signal without removing
the input signals. Typically, 4.6dB SD hysteresis is provided
to prevent chattering.
Signal Detect-Level Set
A programmable signal detect-level set pin (SD
LVL
) sets
the threshold of the input amplitude detection. Connecting
an external resistor between V
CC
and SD
LVL
sets the voltage
at SD
LVL
. This voltage ranges from V
CC
to V
REF
. The
external resistor creates a voltage divider between V
CC
and
V
REF
as shown in Figure 6. If desired, an appropriate
external voltage may be applied rather than using a resistor.
The smaller the external resistor, implying a smaller voltage
difference from SD
LVL
to V
CC
, lowers the SD sensitivity.
Hence, larger input amplitude is required to assert SD.
Typical Operating Characteristics
shows the relationship
between the input amplitude detection sensitivity and the
SD
LVL
setting resistor.
Hysteresis
The SY88983V provides typically 4.6dB SD electrical
hysteresis. By definition, a power ratio measured in dB is
10log(power ratio). Power is calculated as V
2
IN
/R for an
electrical signal. Hence, the same ratio can be stated as
20log(voltage ratio). While in linear mode, the electrical
voltage input changes linearly with the optical power and
hence, the ratios also change linearly. Therefore, the optical
hysteresis in dB is half the electrical hysteresis in dB given
in the data sheet. The SY88983V provides typically 2.3dB
SD optical hysteresis. As the SY88983V is an electrical
device, this data sheet refers to hysteresis in electrical terms.
With 4.6dB SD hysteresis, a voltage factor of 1.7 is required
to assert SD from its de-assert value.
6
SY88983V
Micrel, Inc.
M9999-020205
hbwhelp@micrel.com or (408) 955-1690
February 2005
DATA+
5mV (Min.)
900mV (Max.)
10mV
p-p
(Min.)
1800mV
p-p
(Max.)
DATA
(DATA+) (DATA)
V
IS
(mV)
V
ID
(mV
p-p
)
Figure 1. V
IS
and V
ID
Definition
GND
V
CC
V
CC
0.1µF
0.1µF
50
/D
IN
0.1µF
50
V
REF
D
IN
AC-Coupling
Capacitors
ESD
STRUCTURE
Figure 2. Input Structure
50
GND
V
CC
16mA
/D
OUT
AC-Coupling
Capacitors
Z
0
= 50
Z
0
= 50
V
CC
50 50
50
ESD
STRUCTURE
D
OUT
0.1µF
Figure 3. Output Structure
50
GND
16mA
50
V
CC
16mA
I
CC
ESD
STRUCTURE
Figure 4. Power Supply Current Measurement
SD
5k
V
CC
Figure 5. SD Output Structure
R
SDLVL
SD
LVL
V
CC
V
REF
2.8k
Figure 6. SD
LVL
Setting Circuit

SY88983VMG

Mfr. #:
Manufacturer:
Description:
Limiting Amplifiers 3.3V-5V 3.2 Gbps CML Post Amp
Lifecycle:
New from this manufacturer.
Delivery:
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