MAX1363EUB+T Datasheet MAX1363EUB+, MAX1364EUB+, MAX1363EUB+T | P19-P21

clearing all alarms or by initiating an SMBus alert during

an alarm condition (see the

SMBus Alert

section).

The Delay 2, Delay 1, Delay 0 bits set the speed of

monitoring by changing the delay between conver-

sions. Delay 2, 1, 0 = 000 sets the maximum possible

speed; 001 divides the maximum speed by ~2.

Increasing delay values further divides the previous

speed by two.

INT_EN controls the open-drain INT output. Set INT_EN

to 1 to enable the hardware interrupt. Set INT_EN to 0

to disable the hardware interrupt output. The INT output

tri-states when disabled or when there are no alarms.

The master can also poll the alarm status register at

any time to check the alarm status.

Repeat clocking channel threshold data up to the chan-

nel programmed by CS1 and CS0 (Table 12). For differ-

ential input mode, omit odd channels; the lower and

upper threshold data applies to channel pairs. There is

no need to clock in dummy data for odd (or even)

channels (Table 6).

To disable alarming on a specific channel, set the lower

threshold to 0x800 and the upper threshold to 0x7FF for

bipolar mode, or set the lower threshold to 0x000 and

the upper threshold to 0xFFF for unipolar mode.

MAX1363/MAX1364

4-Channel, 12-Bit System Monitors with Programmable

Trip Window and SMBus Alert Response

______________________________________________________________________________________ 19

Alarm reset, scan

speed, INT_EN ,

(8 bits)

AIN0 thresholds

(24 bits)

AIN1 thresholds

(skip if differential mode, or

CS1, CS0 < 1) (24 bits)

AIN2 thresholds (skip if

CS1, CS0 < 2)

(24 bits)

AIN3 thresholds (skip if differential

mode, or CS1, CS0 < 3)

(24 bits)

Table 9. Monitor-Mode Setup Data Format

RESET

ALARM CH 0

RESET

ALARM CH 1

RESET

ALARM CH 2

RESET

ALARM CH 3

DELAY 2 DELAY 1 DELAY 0 INT_EN

0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1

Table 10. Alarm Reset, Scan Speed Register, and INT_EN Data Format

DELAY 2 DELAY 1 DELAY 0

MONITOR-MODE

CONVERSION RATE

(ksps)

0 0 0 133.0*

001 66.5

010 33.3

011 16.6

100 8.3

101 4.2

110 2.0

111 1.0

Table 11. Delay Settings

When using delay = [0,0,0] in internal reference mode and

AIN3/REF configured as a REF output, the MAX1363/MAX1364

may exhibit a code-dependent gain error due to insufficient

internal reference drive. Gain error caused by this phenomenon

is typically less than 1%FSR (0.1µF C

REF

) and increases with a

larger C

REF

. Avoid this gain error by using an external reference,

, as a reference or use an internal reference with AIN3/REF

as an analog input (see Table 4). Alternatively, choose delay bits

other than [0,0,0] to lower the conversion rate.

BYTE B7 B6 B5 B4 B3 B2 B1 B0 ACKNOWLEDGE

LT11

(MSB)

LT10 LT9 LT8 LT7 LT6 LT5 LT4 ACK

2 LT3 LT2 LT1 LT0 (LSB)

UT11

(MSB)

UT10 UT9 UT8 ACK

3 UT7 UT6 UT5 UT4 UT3 UT2 UT1 UT0 (LSB) ACK

Table 12. Lower and Upper Threshold Data Format

X = Don’t care.

ACK = Acknowledge.

MAX1363/MAX1364

Readback Mode

Select readback mode by setting CS3, CS2 to [1,1] in

the configuration byte. Begin a read operation to start

reading back monitor-setup data. Clock out delay bit

settings, INT_EN bit, and the lower and upper thresh-

olds programmed for each channel. Readback mode

follows exactly the same format as writing to the moni-

tor-setup data, with the exception of the first 4 alarm-

reset bits, which are always 1 (Table 13).

Reading in Monitor Mode

Reading in monitor mode reads back the alarm-status

results as shown in Table 14.

The MAX1363/MAX1364 register pointer loops back to

the beginning of the current-conversion result after

reading the last conversion result. Stop reading at any

time by asserting a STOP condition or NACK.

Note: The MAX1363/MAX1364 do not update the cur-

rent-conversion results register while reading in monitor

mode. Monitor mode resumes after a STOP condition

or NACK.

Alarm-Status Register and Latched-Fault Register

The latched-fault register records a snapshot of the

alarming channel at the instance that a fault condition is

asserted. An alarm-status bit of 1 (Table 15) indicates a

fault, and the data in the latched-fault register of the

corresponding channel contains the conversion result

that caused the alarm to trip. Resetting alarms does not

clear the latched-fault register, thus the latched-fault

high for the given channel.

The current-conversion register contains the most

recent conversion results. If the user attempts to read

past the last result of the current-conversion register,

the MAX1363/MAX1364 wraps back to the beginning of

the current-conversion result.

The latched-fault register and current-conversion regis-

ter follow the data format in the

Reading a Conversion

(

Read Cycle)

section. Register length depends on the

number of conversions in one monitoring sequence.

For example, when channel pairs 0/1 and channels 2/3

are monitored differentially, there are only two conver-

sion results to report. The latched-fault register is 2 x 16

bits long, after which two current-conversion results fol-

low. Likewise, if CS0 and CS1 limit the upper bound of

the channel scan range from CH0 to CH2 in single-

ended mode, the latched-fault register clocks out 3 x

16 bits of data followed by the current-conversion

results, also 3 x 16 bits.

4-Channel, 12-Bit System Monitors with Programmable

Trip Window and SMBus Alert Response

20 ______________________________________________________________________________________

ALARM RESET/SCAN SPEED

AIN0

THRESHOLDS

AIN1 THRESHOLDS

(SKIP IF DIFFERENTIAL

MODE OR CS1, CS0 < 1)

AIN2 THRESHOLDS

(SKIP IF CS1, CS0 < 2)

AIN3 THRESHOLDS

(SKIP IF DIFFERENTIAL

MODE OR CS1, CS0 < 3)

1 1 1 1 D2 D1 D0 INT 24 bits 24 bits 24 bits 24 bits

Table 13. Readback-Mode Format

ALARM-STATUS REGISTER LATCHED-FAULT REGISTER CURRENT-CONVERSION RESULTS

8 bits 16, 32, 48, or 64 bits 16, 32, 48, or 64 bits

Table 14. Reading in Monitor-Mode Data Format

CH0 UP CH0 LOW CH1 UP CH1 LOW CH2 UP CH2 LOW CH3 UP CH3 LOW

0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1

Table 15. Alarm-Status Register

0 = Not-alarm condition.

1 = Alarm condition.

AIN0 AIN1 AIN2 AIN3

16-bit read 16-bit read 16-bit read 16-bit read

Table 16. Latched-Fault and Current-

Conversion Register

Resetting Alarm

Reset alarms by writing to monitor-setup data. See the

Configuring Monitor Mode

section and Table 10.

SMBus Alert

The SMBus-alert feature provides a quick method to

identify alarming devices on a shared interrupt. Upon

receiving an interrupt signal, the host µC can broadcast

a receive byte request to the alert-response slave

address (0001100). Any slave device that generated an

interrupt attempts to identify itself by putting its own

address on the bus. The alert response can activate

several different slave devices simultaneously. If more

than one slave attempts to respond, bus arbitration

rules apply, and the device with the lower address wins

as a consequence of the open-collector bus. The losing

device does not generate an acknowledgement and

continues to hold the alert line low until serviced.

Successful reading of the alert response address de-

asserts INT.

When the MAX1363/MAX1364 successfully send the

C address, it can resume and reassert INT right away

(if the fault is still present). To prevent this from happen-

ing, monitor mode does not resume until after the host

controller resets the alarm in the alarm status register.

Any alarms not cleared when the device resumes moni-

tor mode reassert INT.

Transfer Functions

Output data coding for the MAX1363/MAX1364 is bina-

ry in unipolar mode and two’s complement in bipolar

mode with 1 LSB = V

REF

/ 2

, where N is the number of

bits. Code transitions occur halfway between succes-

sive-integer LSB values. Figures 14 and 15 show the

transfer functions for unipolar and bipolar operations,

respectively.

Layout, Grounding, and Bypassing

Only use PC boards. Wire-wrap configurations are not

recommended since the layout should ensure proper

separation of analog and digital traces. Do not run ana-

log and digital lines parallel to each other, and do not

layout digital signal paths underneath the ADC pack-

age. Use separate analog and digital PC board ground

sections with only one star point (Figure 16).

High-frequency noise in the power supply (V

) could

influence the proper operation of the ADC’s fast com-

parator. Bypass V

to the star ground with a network of

two parallel capacitors, 0.1µF and 4.7µF, located as

close as possible to the MAX1363/MAX1364 power sup-

ply. Minimize capacitor lead length for best supply noise

rejection. For extremely noisy supplies, add an attenua-

tion resistor (5Ω) in series with the power supply.

MAX1363/MAX1364

4-Channel, 12-Bit System Monitors with Programmable

Trip Window and SMBus Alert Response

______________________________________________________________________________________ 21

111...111

OUTPUT CODE

FS = REF + GND

ZS = GND

FULL-SCALE

TRANSITION

111...110

100...010

100...001

100...000

011...111

011...110

011...101

000...001

000...000

512

INPUT VOLTAGE (LSB)(GND)

1 LSB =

REF

1024

FS - 0.5 LSB

Figure 14. Unipolar Transfer Function

011...111

OUTPUT CODE

ZS = AIN-

011...110

000...010

000...001

000...000

111...111

111...110

111...101

100...001

100...000

AIN-

INPUT VOLTAGE (LSB)

+FS - 1 LSB

1 LSB =

REF

1024

AIN- ≥

REF

FS =

REF

+ AIN-

-FS =

-V

REF

+ AIN-

-FS + 0.5 LSB

Figure 15. Bipolar Transfer Function

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MAX1363EUB+T

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Analog to Digital Converters - ADC 12-Bit 4Ch 133ksps 3.6V Precision ADC

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