unsuccessful data transfers. An unsuccessful data trans-
fer happens if a receiving device is busy or if a system
fault has occurred. In the event of an unsuccessful data
transfer, the bus master reattempts communication at a
later time.
Slave Address
The MAX1363/MAX1364 have a 7-bit I
2
C slave
address. The slave address is selected using A0. The
MAX1363/MAX1364 (EUB, MEUB, and LEUB) have
three base address options, allowing up to six devices
concurrently per I
2
C bus (see Table 1).
The MAX1363/MAX1364 continuously wait for a START
condition followed by its slave address. When the device
recognizes its slave address, it is ready to accept or
send data depending on the R/W bit (Figure 6).
HS I
2
C Mode
At power-up, the MAX1363/MAX1364 bus timing is set
for fast mode (F/S mode, up to 400kHz I
2
C clock), which
limits the conversion rate to approximately 22ksps.
Switch to high-speed mode (HS mode, up to 1.7MHz
I
2
C clock) to achieve conversion rates up to 94.4ksps.
The MAX1363/MAX1364 convert up to 133ksps in moni-
tor mode, regardless of I
2
C mode. If conversion results
are unread, I
2
C bandwidth limitations do not apply (see
the
Monitor Mode
section).
Select HS mode by addressing all devices on the bus
with the HS-mode master code 0000 1XXX (X = don’t
care). After successfully receiving the HS-mode master
code, the MAX1363/MAX1364 issue a NACK, allowing
SDA to be pulled high for one clock cycle (Figure 7).
After the NACK, the MAX1363/MAX1364 operate in HS
mode. Send a repeated START (Sr) followed by a slave
address to initiate HS-mode communication. If the mas-
ter generates a STOP condition, the MAX1363/
MAX1364 return to F/S mode. Use a repeated START
condition (Sr) in place of a STOP condition to leave the
bus active and the mode unchanged.
MAX1363/MAX1364
4-Channel, 12-Bit System Monitors with Programmable
Trip Window and SMBus Alert Response
______________________________________________________________________________________ 13
011 1000R/WACK
SLAVE ADDRESS
S
SCL
SDA
123456789
Figure 6. MAX1363/MAX1364 Slave Address Byte
A0 STATE SUFFIX ADDRESS
Low EUB 0110100
High EUB 0110101
Low MEUB 0110110
High MEUB 0110111
Table 1. I
2
C Slave Selection Table
000 10XXXNACK
HS-MODE MASTER CODE
SCL
SDA
S Sr
F/S MODE HS MODE
Figure 7. F/S-Mode to HS-Mode Transfer
MAX1363/MAX1364
4-Channel, 12-Bit System Monitors with Programmable
Trip Window and SMBus Alert Response
14 ______________________________________________________________________________________
START
CONDITION
START
ADDRESS
FROM THE MASTER
CONFIGURATION
BYTE FROM THE MASTER
SETUP
BYTE FROM THE MASTER
0 A A A STOP
R/W BIT FROM
THE MASTER
Figure 8. Example of Writing Setup and Control Bytes
START
CONDITION
START
ADDRESS
FROM THE MASTER
SETUP BYTE
FROM THE MASTER
ALARM RESET, SCAN
SPEED, BYTE FROM MASTER
0A 1A A
CH 0 LT [11:4] BYTE
CH 0 LT [3:0];
UT [11:8] BYTE
CH 1 LT [11:4] BYTECH 0 UT [7:0] BYTEAAAASTOP
R/W BIT FROM
THE MASTER
Figure 9. Example of Extended Setup Byte Writing
BIT NAME DESCRIPTION
7(MSB) CONFIG The configuration byte always starts with 0.
6 SCAN1
5 SCAN0
SCAN1, SCAN0 = [0,0], scans from channel 0 to the upper channel chosen by CS1, CS0.
SCAN1, SCAN0 = [0,1], converts a single channel chosen by CS1, CS0 eight times.
SCAN1, SCAN0 = [1,0] monitor mode monitors from channel 0 to the upper channel chosen by CS1, CS0.
SCAN1, SCAN0 = [1,1], single channel conversion for the channel is chosen by CS0, CS1.
4CS3
3CS2
CS3, CS2 = [1,1] enables readback of monitor-mode setup data.
2CS1
1CS0
Selects the upper limit of the channel range used for the conversion sequence in scan modes SCAN = [0,0]
and monitor modes SCAN = [1,0].
Selects the conversion channel when SCAN = [0,1] or when SCAN = [1,1].
(Tables 5 and 6)
0 SE/DIF
1 = single-ended inputs.
0 = differential inputs.
AIN0 and AIN1 form the first differential pair and AIN2 and AIN3 form the second differential pair. (See Tables
4 and 5.)
Selects single-ended or differential conversions. In single-ended mode, input-signal voltages are referenced
to GND. In differential mode, the voltage difference between two channels is measured.
When single-ended mode is used, the MAX1363/MAX1364 perform unipolar conversions regardless of the
UNI/BIP bit in the setup byte.
(Table 7)
Table 2. Configuration Byte Format*
*
Power-on defaults: 0x01
Software Description
Configuration/Setup Bytes (Write Cycle)
A write cycle begins with the bus master issuing a
START condition followed by 7 address bits and a write
bit (R/W = 0). If the address byte is successfully
received, the MAX1363/MAX1364 (slave) issue an ACK.
The master then writes to the slave. If the most signifi-
cant bit (MSB) is 1, the slave recognizes the received
byte as the setup byte (Table 4). If the MSB is 0, the
slave recognizes that byte as the configuration byte
(Table 2). Write to the configuration byte before writing
to the setup byte (Figure 8). If enabling RESET in the
setup byte, rewrite the configuration byte after writing
the setup byte, since RESET clears the contents of the
configuration byte back to the power-up state.
When the monitor-setup bit of the setup byte is set to 1,
writing extends up to 13 bytes to clock in monitor-setup
data. Terminate writing monitor-setup data at any time
by issuing a STOP or repeated START condition. If the
slave receives a byte successfully, it issues an ACK
(Figure 9).
Note: When operating in HS mode, a STOP condition
returns the bus into F/S mode (see the
HS I
2
C Mode
section).
Automatic Shutdown
AutoShutdown occurs between conversions when the
MAX1363/MAX1364 are idle. When operating in exter-
nal clock mode, issue a STOP, NACK, or repeated
START condition to place the devices in idle mode and
benefit from automatic shutdown. A STOP condition is
not necessary in internal clock mode for automatic
shutdown because power-down occurs once all con-
tents are written memory. Shutdown reduces supply
current to less than 0.5µA (external reference mode,
typ) and 300µA (internal reference mode, typ).
When idle, the MAX1363/MAX1364 continuously wait
for a START condition followed by their slave address.
Upon reading a valid address byte, the MAX1363/
MAX1364 power up. The internal reference requires
10ms to wake up. Therefore, power up the internal ref-
erence 10ms prior to conversion or leave the reference
continuously powered. Wake-up is transparent when
using an external reference or V
DD
as the reference.
Automatic shutdown results in dramatic power savings,
particularly at slow conversion rates with internal clock.
For example, using an external reference at a conver-
sion rate of 10ksps, the average supply current for the
MAX1363 is 60µA (typ) and drops to 6µA (typ) at
1ksps. At 0.1ksps, the average supply current is just
1µA. Table 3 shows AIN3/REF configuration and refer-
ence power-down state.
Scan Modes
SCAN1 and SCAN0 of the configuration byte set the
scan-mode configuration. When configuring AIN3/REF
for reference input or output (SEL0 = 1), AIN3/REF is
excluded from a multichannel scan. The scanned
results write to memory in the same order as the con-
version. Start a conversion sequence by initiating a
read with the desired scan mode. Read the results from
memory in the order they were converted (see the
Reading a Conversion (Read Cycle)
section).
Selecting channel scan mode [0,0] starts converting
from channel 0 up to the channel chosen by CS1, CS0.
Selecting channel scan mode [0,1] converts the chan-
nel selected by CS1, CS0 eight times and returns eight
consecutive results.
Selecting monitor mode [1,0] initiates a continuous con-
version scan sequence from channel 0 to the channel
selected by CS1, CS0. See the
Monitor Mode
section
for more details.
Selecting channel scan mode [1,1] performs a single
conversion on the channel selected by CS1, CS0 and
returns the result.
Reading a Conversion (Read Cycle)
Initiate a read cycle to start a conversion sequence and
to obtain conversion results. See the
Scan Modes
section for details on the channel-scan sequence. Read
MAX1363/MAX1364
4-Channel, 12-Bit System Monitors with Programmable
Trip Window and SMBus Alert Response
______________________________________________________________________________________ 15
SEL1 SEL0
INT REF
POWER-DOWN
REFERENCE VOLTAGE AIN3/REF
INTERNAL
REFERENCE STATE
00 X V
DD
Analog input Always off
0 1 X External reference Reference input Always off
1 0 0 Internal reference Analog input Always off
1 0 1 Internal reference Analog input Always on
1 1 0 Internal reference Reference output Always off
1 1 1 Internal reference Reference output Always on
Table 3. Reference Voltage and AIN3/REF Format

MAX1364EUB+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Analog to Digital Converters - ADC 12-Bit 4Ch 133ksps 5.5V Precision ADC
Lifecycle:
New from this manufacturer.
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