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DG401BDY-T1

P1-P3P4-P6P7-P9P10-P12P13-P14
Vishay Siliconix
DG401B, DG403B, DG405B
Document Number: 73069
S11-0179-Rev. B, 07-Feb-11
www.vishay.com
1
Low-Power, High-Speed CMOS Analog Switches
FEATURES
• 44 V supply max rating
• ± 15 V analog signal range
• On-resistance - R
DS(on)
: 23
• Low leakage - I
D(on)
: 40 pA
• Fast switching - t
ON
: 100 ns
• Upgrade to DG401B, DG403B, DG405B
• TTL, CMOS compatible
• Single supply capability
BENEFITS
• Wide dynamic range
• Break-before-make switching action
(DG403B only)
• Simple interfacing
APPLICATIONS
• Audio and video switching
• Sample-and-hold circuits
• Test equipment
• PBX, PABX
DESCRIPTION
The DG401B, DG403B, DG405B monolithic analog switches
are replacements for the popular DG401/403/405 analog
switches and provide improved performance, combining
high speed (t
ON
: 100 ns, typ) with low power consumption
make the DG401B series ideal for portable and battery
powered applications.
Built on the Vishay Siliconix proprietary high-voltage silicon-
gate process to achieve high voltage rating and superior
switch on/off performance, break-before-make is
guaranteed for the SPDT configurations.
Each switch conducts equally well in both directions when
on, and blocks up to 30 V peak-to-peak when off.
On-resistance is very flat over the full ± 15 V analog range.
The DG401B has two independent SPST switches. The
DG403B has four SPST switches in NO/NC combinations.
The DG405B has four switches in two SPST pairs (see
Functional Block Diagrams and Pin Configurations on pages
1 and 2.)
The DG401B, DG403B, DG405B is available in both 16-pin
plastic dip and 16-pin SOIC packages.
As a committed partner to the community and the
environment, Vishay Siliconix manufactures this product
with the lead (Pb)-free device terminations. For analog
switching products manufactured with 100 % matte tin
device terminations, the lead (Pb)-free “-E3” suffix is being
used as a designator.
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
Two SPST Switches per Package
Logic “0” 0.8 V
Logic “1” 2.4 V
DG401B
NC GND
NC NC
NC V+
NC IN
2
D
2
S
2
D
1
S
1
NC
Dual-In-Line and SOIC
IN
1
NC V-
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Top View
TRUTH TABLE
Logic Switch
0 OFF
1ON
www.vishay.com
2
Document Number: 73069
S11-0179-Rev. B, 07-Feb-11
Vishay Siliconix
DG401B, DG403B, DG405B
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
Four SPST Switches in Two Pairs per Package
Logic “0” 0.8 V
Logic “1” 2.4 V
Four SPST Switches in Two Pairs per Package
Logic “0” 0.8 V
Logic “1” 2.4 V
DG403B
D
1
S
1
NC
Dual-In-Line and SOIC
IN
1
D
3
V-
S
3
GND
S
4
NC
D
4
V+
NC
IN
2
D
2
S
2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Top View
TRUTH TABLE
Logic
SW
1
, SW
2
SW
3
, SW
4
0 OFF ON
1ONOFF
DG405B
D
1
S
1
NC
Dual-In-Line and SOIC
IN
1
D
3
V-
S
3
GND
S
4
NC
D
4
V+
NC IN
2
D
2
S
2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Top View
TRUTH TABLE
Logic Switch
0 OFF
1ON
ORDERING INFORMATION
Standard
Commercial
Part Number
Lead (Pb)-free
Commercial
Part Number
Package
Temperature
Range
DG401BDJ DG401BDJ-E3
16-Pin Plastic Dip
- 40 to 85 °C
DG403BDJ DG403BDJ-E3
DG405BDJ DG405BDJ-E3
DG401BDY DG401BDY-E3
16-Pin Narrow SOICDG403BDY DG403BDY-E3
DG405BDY DG405BDY-E3
DG401BDY-T1 DG401BDY-T1-E3
16-Pin Narrow SOIC With Tape and
Reel
DG403BDY-T1 DG403BDY-T1-E3
DG405BDY-T1 DG405BDY-T1-E3
Document Number: 73069
S11-0179-Rev. B, 07-Feb-11
www.vishay.com
3
Vishay Siliconix
DG401B, DG403B, DG405B
Notes:
a. Signals on S
X
, D
X
, or IN
X
exceeding V+ or V- will be clamped by internal diodes. Limit forward diode current to maximum current ratings.
b. All leads welded or soldered to PC board.
c. Derate 6 mW/°C above 75 °C.
d. Derate 7.6 mW/°C above 75 °C.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS
Parameter Symbol Limit Unit
V+ to V- 44
V
GND to V- 25
Digital Inputs
a
, V
S
, V
D
(V-) - 0.3 V to (V+) + 0.3 V or
30 mA, whichever occurs first
Current (Any Terminal) Continuous 30
mA
Current, S or D (Pulsed 1 ms 10 % duty) 100
Storage Temperature (DJ, DY Suffix) - 65 to 125 °C
Power Dissipation (Package)
b
16-Pin Plastic DIP
c
450
mW
16-Pin SOIC
d
600
SPECIFICATIONS
a
Parameter Symbol
Test Conditions
Unless Specified
V+ = 15 V, V- = - 15 V
V
IN
= 2.4 V, 0.8 V
f
Temp.
b
Limits
- 40 °C to 85 °C
Unit
Min.
d
Typ.
c
Max.
d
Analog Switch
Analog Signal Range
e
V
ANALOG
Full -15 15 V
Drain-Source
On-Resistance
R
DS(on)
I
S
= - 10 mA, V
D
= ± 10 V
V+ = 13.5 V, V- = - 13.5 V
Room
Full
23 45
55
Drain-Source
On-Resistance
R
DS(on)
I
S
= - 10 mA, V
D
= ± 5 V, 0 V
V+ = 16.5 V, V- = - 16.5 V
Room
Full
0.72 3
5
Switch Off Leakage Current
I
S(off)
V+ = 16.5, V- = - 16.5 V
V
D
= ± 15.5 V, V
S
= ± 15.5 V
Room
Hot
- 0.5
- 5
- 0.01 0.5
5
nAI
D(off)
Room
Hot
- 0.5
- 5
- 0.01 0.5
5
Channel On Leakage Current I
D(on)
V+ = 16.5 V, V- = - 16.5 V
V
S
= V
D
= ± 15.5 V
Room
Hot
- 1
- 10
- 0.04 1
10
Digital Control
Input Current V
IN
Low I
IL
V
IN
under test = 0.8 V, all other = 2.4 V Full - 1 0.005 1
µA
Input Current V
IN
High I
IH
V
IN
under test = 2.4 V, all other = 0.8 V Full - 1 0.005 1
Dynamic Characteristics
Tu r n - On T im e t
ON
R
L
= 300 , C
L
= 35 pF
see figure 2
Room 100 150
ns
Turn-Off Time t
OFF
Room 60 100
Break-Before-Make Time Delay
(DG403B)
t
D
R
L
= 300 , C
L
= 35 pF Room 5 12
Charge Injection Q C
L
= 10 000 pF, V
gen
= 0 V, R
gen
= 0 Room 60 pC
Off Isolation Reject Ratio OIRR
R
L
= 100 , C
L
= 5 pF, f =1 MHz
Room - 81.7
dB
Channel-to-Channel Crosstalk X
TA LK
Room - 94.8
Source Off Capacitance C
S(off)
f = 1 MHz, V
S
= 0 V
Room 12
pFDrain Off Capacitance C
D(off)
Room 12
Channel On Capacitance C
D
, C
S(on)
Room 39
P1-P3P4-P6P7-P9P10-P12P13-P14

DG401BDY-T1

Mfr. #:
Buy DG401BDY-T1
Manufacturer:
Vishay / Siliconix
Description:
Analog Switch ICs RECOMMENDED ALT 781-DG401BDY-T1-E3
Lifecycle:
New from this manufacturer.
Delivery:
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Payment:
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