11
Figure 20. Energy Dissipated in the HCPL-314J
and for Each IGBT Switching Cycle.
=
24 V – 5 V
0.6A
= 32 Ω
Rg ≥
V
CC
– V
OL
I
OLPEAK
LED Drive Circuit Considerations for Ultra
High CMR Performance
Without a detector shield, the domi-
nant cause of optocoupler CMR
failure is capacitive coupling from
the input side of the optocoupler,
through the package, to the detec-
tor IC as shown in Figure 21. The
HCPL-314J improves CMR perfor-
mance by using a detector IC with an
optically transparent Faraday shield,
which diverts the capacitively cou-
pled current away from the sensi-
tive IC circuitry. However, this shield
does not eliminate the capacitive
coupling between the LED and opt-
ocoupler pins 5-8 as shown in Figure
22. This capacitive coupling causes
perturbations in the LED current
during common mode transients
and becomes the major source of
CMR failures for a shielded optocou-
pler. The main design objective of a
high CMR LED drive circuit becomes
keeping the LED in the proper state
(on or o ) during common mode
transients. For example, the recom-
mended application circuit (Figure
19), can achieve 10 kV/µs CMR while
minimizing component complexity.
Techniques to keep the LED in the
proper state are discussed in the
next two sections.
Selecting the Gate Resistor (Rg)
Step 1: Calculate R
g
minimum from the I
OL
peak specication. The IGBT and
Rg in Figure 24 can be analyzed as a simple RC circuit with a voltage sup-
plied by the HCPL-314J.
The V
OL
value of 5 V in the previous equation is the V
OL
at the peak current
of 0.6A. (See Figure 6).
Step 2: Check the HCPL-314J power dissipation and increase Rg if necessary.
The HCPL-314J total power dissipation (P
T
) is equal to the sum of the emit-
ter power (P
E
) and the output power (P
O
).
PT = PE + PO
PE = IF • VF • Duty Cycle
PO = PO(BIAS) + PO(SWITCHING) = ICC • VCC + ESW (Rg,Qg)• f
= (ICCBIAS + KICC • Qg • f) • VCC + ESW (Rg,Qg) • f
where KICC • Qg • f is the increase in I
CC
due to switching and KICC is a con-
stant of 0.001 mA/(nC*kHz). For the circuit in Figure 19 with IF (worst case)
= 10 mA, Rg = 32 Ω, Max Duty Cycle = 80%, Qg = 100 nC, f = 20 kHz and
T
AMAX
= 85°C:
PE = 10 mA • 1.8 V • 0.8 = 14 mW
PO = (3 mA + (0.001 mA/(nC • kHz)) • 20 kHz • 100 nC) • 24 V + 0.4 µJ • 20 kHz
= 128 mW
< 260 mW (PO(MAX) @ 85°C)
The value of 3 mA for I
CC
in the previous equation is the max. I
CC
over entire
operating temperature range.
Since PO for this case is less than PO(MAX), Rg = 32 Ω is alright for the power
dissipation.
Esw – ENERGY PER SWITCHING CYCLE – µJ
0
0
Rg – GATE RESISTANCE –
100
1.5
20
4.0
40
1.0
60 80
3.5
Qg = 50 nC
Qg = 100 nC
Qg = 200 nC
Qg = 400 nC
3.0
2.0
0.5
2.5
