Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 1
Rev. F
08/25/2014
Copyright © 2014 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-
est version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason-
ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications
unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
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c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
IS62WV25616ALL
IS62WV25616BLL
256K x 16 LOW VOLTAGE,
ULTRA LOW POWER CMOS STATIC SRAM
FEATURES
• High-speedaccesstime:55ns,70ns
• CMOSlowpoweroperation
36 mW (typical) operating
9µW(typical)CMOSstandby
• TTLcompatibleinterfacelevels
• Singlepowersupply
1.65V--2.2V V
dd (IS62WV25616ALL)
2.5V--3.6V V
dd (IS62WV25616BLL)
• Fullystaticoperation:noclockorrefresh
required
• Threestateoutputs
• Datacontrolforupperandlowerbytes
• Industrialtemperatureavailable
• Lead-freeavailable
DESCRIPTION
TheISSIIS62WV25616ALL/IS62WV25616BLLarehigh-
speed,lowpower,4MbitSRAMsorganizedas256Kwords
by 16 bits. It is fabricated using ISSI's high-performance
CMOStechnology.Thishighlyreliableprocesscoupledwith
innovative circuit design techniques, yields high-performance
and low power consumption devices.
When CS1isHIGH(deselected)orwhen CS1 is LOW and
both LB and UBareHIGH,thedeviceassumesastandby
mode at which the power dissipation can be reduced down
withCMOSinputlevels.
Easy memory expansion is provided by using Chip Enable
andOutputEnableinputs.TheactiveLOWWriteEnable(WE)
controls both writing and reading of the memory. A data byte
allows Upper Byte (UB)andLowerByte(LB) access.
TheIS62WV25616ALL/IS62WV25616BLLarepackaged
intheJEDECstandard44-PinTSOP(TYPEII) and 48-pin
miniBGA(6mmx8mm).
FUNCTIONAL BLOCK DIAGRAM
AUGUST 2014
A0-A17
CS1
OE
WE
256K x 16
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
V
DD
I/O
DATA
CIRCUIT
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
UB
LB