10
LT1636
1636fc
TYPICAL PERFOR A CE CHARACTERISTICS
UW
CHANGE IN INPUT OFFSET VOLTAGE
(100µV/DIV)
Open-Loop Gain
0V 10V
OUTPUT VOLTAGE (5V/DIV)
A
B
C
C
1636 G24
V
S
= ±15V
A
V
= –1
1636 G25
A: R
L
= 2k
B: R
L
= 10k
C: R
L
= 50k
Large-Signal Response
V
S
= ±15V
A
V
= 1
1636 G26
Small-Signal Response
APPLICATIONS INFORMATION
WUU
U
cause the voltage at which operation switches from the
PNP stage to the NPN stage to move towards V
+
. The input
offset voltage of the NPN stage is untrimmed and is
typically 600µV.
A Schottky diode in the collector of each NPN transistor of
the NPN input stage allows the LT1636 to operate with
either or both of its inputs above V
+
. At about 0.3V above
V
+
the NPN input transistor is fully saturated and the input
bias current is typically 3µA at room temperature. The
input offset voltage is typically 600µV when operating
above V
+
. The LT1636 will operate with its input 44V above
V
–
regardless of V
+
.
The inputs are protected against excursions as much as
22V below V
–
by an internal 1k resistor in series with each
input and a diode from the input to the negative supply.
There is no output phase reversal for inputs up to 5V below
V
–
. There are no clamping diodes between the inputs and
the maximum differential input voltage is 44V.
Output
The output voltage swing of the LT1636 is affected by in-
put overdrive as shown in the typical performance curves.
When monitoring voltages within 100mV of V
+
, gain
should be taken to keep the output from clipping.
The output of the LT1636 can be pulled up to 27V beyond
V
+
with less than 1nA of leakage current, provided that V
+
is less than 0.5V.
Supply Voltage
The positive supply pin of the LT1636 should be bypassed
with a small capacitor (about 0.01µF) within an inch of the
pin. When driving heavy loads an additional 4.7µF electro-
lytic capacitor should be used. When using split supplies,
the same is true for the negative supply pin.
The LT1636 is protected against reverse battery voltages
up to 27V. In the event a reverse battery condition occurs,
the supply current is less than 1nA.
When operating the LT1636 on total supplies of 20V or
more, the supply must not be brought up faster than 1µs.
This is especially true if low ESR bypass capacitors are
used. A series RLC circuit is formed from the supply lead
inductance and the bypass capacitor. 5Ω of resistance in
the supply or the bypass capacitor will dampen the tuned
circuit enough to limit the rise time.
Inputs
The LT1636 has two input stages, NPN and PNP (see
Simplified Schematic), resulting in three distinct operat-
ing regions as shown in the Input Bias Current vs Common
Mode typical performance curve.
For input voltages about 0.8V or more below V
+
, the PNP
input stage is active and the input bias current is typically
–4nA. When the input voltage is about 0.5V or less from
V
+
, the NPN input stage is operating and the input bias
current is typically 10nA. Increases in temperature will
A
B
–10VV
S
= ±15V
