9
AT24C164
0105H–SEEPR–1/04
Device Addressing The AT24C164 requires an 8-bit device address word following a start condition to
enable the chip for read or write operations (refer to Figure 1). The most significant bit
must be a one followed by the A2, A1 and A0 device select bits (the A1 bit must be the
compliment of the A1 input pin signal). The next 3 bits are used for memory block
addressing and select one of the eight 256 x 8 memory blocks. These bits should be
considered the three most significant bits of the data word address. The eighth bit of the
device address is the read/write select bit. A read operation is selected if this bit is high
or a write operation is selected if this bit is low.
Upon a compare of the device address, the EEPROM will output a zero. If a compare is
not made, the chip will return to a standby state.
Write Operations BYTE WRITE: A write operation requires an 8-bit data word address following the
device address word and acknowledgment. Upon receipt of this address, the EEPROM
will again respond with a zero and then clock in the first 8-bit data word. Following
receipt of the 8-bit data word, the EEPROM will output a zero and the addressing
device, such as a microcontroller, must terminate the write sequence with a stop condi-
tion. At this time the EEPROM enters an internally-timed write cycle, t
WR
, to the
nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will
not respond until the write is complete (refer to Figure 2).
PAGE WRITE: The AT24C164 is capable of a 16-byte page write. A page write is initi-
ated the same as a byte write, but the microcontroller does not send a stop condition
after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt
of the first data word, the microcontroller can transmit up to fifteen more data words. The
EEPROM will respond with a zero after each data word received. The microcontroller
must terminate the page write sequence with a stop condition (refer to Figure 3).
The data word address lower 4 bits are internally incremented following the receipt of
each data word. The higher data word address bits are not incremented retaining the
memory page row location. When the word address, internally generated, reaches the
page boundary, the following byte is placed at the beginning of the same page. If more
than sixteen data words are transmitted to the EEPROM, the data word address will “roll
over” and previous data will be overwritten.
ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the
EEPROM inputs are disabled, acknowledge polling can be initiated. This involves send-
ing a start condition followed by the device address word. The read/write bit is
representative of the operation desired. Only if the internal write cycle has completed
will the EEPROM respond with a zero allowing the read or write sequence to continue.
