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LSN2-T/30-D12-C

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
LSN2-T/30-D12 Series
DOSA-SIP, 30A POL DC/DC Converters
MDC_LSN2-T/30-D12 Series.C01Δ Page 10 of 16
www.murata-ps.com/support
Figure 11. Self-Ramping Power Up
If the power up/down timing needs to be closely controlled, each POL must
be characterized for start-up and down times. These often vary—one POL may
stabilize in 15 milliseconds whereas another takes 50 mS. Another problem is
that the sequencing controller itself must be “already running” and stabilized
before starting up other circuits. If there is a glitch in the system, the power
up/down sequencer could get out of step with possible disastrous results.
Lastly, changing the timing may require reprogramming the logic sequencer or
rewriting software.
Sequence/Track Input
A different power sequencing solution is employed on the LSN2-T/30-D12 DC/DC
converter. After external input power is applied and the converter stabilizes, a
high impedance Sequence/Track input pin accepts an external analog voltage.
The output power voltage will then track this Sequence/Track input at a one-to-
one ratio up to the nominal set point voltage for that converter. This Sequenc-
ing input may be ramped, delayed, stepped or otherwise phased as needed for
the output power, all fully controlled by the user’s simple external circuits. As a
direct input to the converter’s feedback loop, response to the Sequence/Track
input is very fast (milliseconds).
By properly controlling this Sequence pin, most operations of the discrete
On/Off logic sequencer may be duplicated. The Sequence pin system does not
use the converter’s Enable On/Off control (unless it is a master emergency shut
down system).
Power Phasing Architectures
Observe the simplifi ed timing diagrams in this section. There are many pos-
sible power phasing architectures and these are just some examples to help
you analyze your system. Each application will be different. Multiple output
voltages may require more complex timing than that shown here.
These diagrams illustrate the time and slew rate relationship between two
typical power output voltages. Generally the Master will be a primary power
voltage in the system which must be present fi rst or coincident with any
Slave power voltages. The Master output voltage is connected to the Slave’s
Sequence input, either by a voltage divider, divider-plus-capacitor or some
other method.
Several standard sequencing architectures are prevalent. They are con-
cerned with three factors:
■
The time relationship between the Master and Slave voltages
■
The voltage difference relationship between the Master and Slave.
■
The voltage slew rate (ramp slope) of each converter’s output.
For most systems, the time relationship is the dominant factor. The voltage
difference relationship is important for systems very concerned about possible
latchup of programmable devices or overdriving ESD diodes. Lower slew rates
avoid overcurrent shutdown during bypass cap charge-up.
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Figure 13. Sequence/Track Simplifi ed Equivalent Schematic
LSN2-T/30-D12 Series
DOSA-SIP, 30A POL DC/DC Converters
MDC_LSN2-T/30-D12 Series.C01Δ Page 11 of 16
www.murata-ps.com/support
In Figure 10, two POLs ramp up at the same rate until they reach their
different respective fi nal set point voltages. During the ramp, their voltages
are nearly identical. This avoids problems with large currents fl owing between
logic systems which are not initialized yet. Since both end voltages are differ-
ent, each converter reaches it’s setpoint voltage at a different time.
Figure 12 shows two POLs with different slew rates in order to reach differ-
ing fi nal voltages at about the same time.
Operation
To use the Sequence pin after power start-up stabilizes, apply a rising external
voltage to the Sequence input. As the voltage rises, the output voltage will
track the Sequence input (gain = 1). The output voltage will stop rising when it
reaches the normal set point for the converter. The Sequence input may option-
ally continue to rise without any effect on the output. Keep the Sequence input
voltage below the converter’s input supply voltage.
Use a similar strategy on power down. The output voltage will stay constant
until the Sequence input falls below the set point.
Any strategy may be used to deliver the power up/down ramps. The circuits
below show simple RC networks but you may also use operational amplifi ers,
D/A converters, etc.
Circuits
The circuits shown in Figures 5 through 13 introduce several concepts when
using these Sequencing controls on Point-of-Load (POL) converters. These
circuits are only for reference and are not intended as fi nal designs ready for
your application. Also, numerous connections are omitted for clarity.
Figure 10 shows a basic Master (POL A) and Slave (POL B) connected so that
the POL B ramps up identically to POL A as shown in timing diagram Figure6.
RCnetwork R1 and C1 charge up at a rate set by the R1-C1 time constant,
giving a roughly linear ramp. As POL A reaches 3.3V out (the setpoint of POLB),
POL B will stop rising. POL A then continues rising until it reaches 5V.
R1 should be selected so that it is signifi cantly smaller than the internal
bias current resistor from the Sequence pin. Start with a value of 20 Kilohms.
In Figure 10, we assume that the critical phase is only on power up therefore
there is no provision for ramped power down.
Figure 11 shows a single POL and the same RC network. However we have
added a small FET at Q1 to function as an up/down control. When V
IN power is
fi rst applied to the POL, Q1 is biased on, shorting out the Sequence pin. When
Q1’s gate is biased off, R1 now charges C1 and the POL’s output now ramps up
at the R1-C1 slew rate. Note that Q1’s gate would typically be controlled from
some external digital logic.
If you wish to have a ramped power down (rather than a step down), add a
small resistor in series with Q1’s drain.
Figure 12 shows both a RC ramp on Master POL A and a proportional track-
ing divider (R2 and R3) on POL B. We have also added an optional very small
noise fi lter cap at C2. Figure 12’s circuit corresponds roughly to Figure 7’s
timing for power up.
Guidelines for Sequence/Track Applications
[1] Leave the converter’s On/Off Enable control (if installed) in the On setting.
Normally, you should just leave the On/Off pin open.
[2] Allow the converter to stabilize (typically less than 20 mS after +V
IN power
on) before raising the Sequence input. Also, if you wish to have a ramped
power down, leave +V
IN powered all during the down ramp. Do not simply
shut off power.
[3] If you do not plan to use the Sequence/Track pin, leave it open.
[4] Observe the Output slew rate relative to the Sequence input. A rough
guide is 2 Volts per millisecond maximum slew rate. If you exceed this
slew rate on the Sequence pin, the converter will simply ramp up at
it’s maximum output slew rate (and will not necessarily track the faster
Sequence input). The reason to carefully consider the slew rate limitation
is in case you want two different POL’s to precisely track each other.
[5] Be aware of the input characteristics of the Sequence pin. The high input
impedance affects the time constant of any small external ramp capacitor.
And the bias current will slowly charge up any external caps over time
if they are not grounded. The internal pull up resistor to +V
IN is typically
400Kilohms to 1 Megohm.
Notice in the simplifi ed Sequence/Track equivalent circuit (Figure 13) that
a blocking diode effectively disconnects this circuit when the Sequence/
Track pin is left open.
[6] Allow the converter to eventually achieve its full rated setpoint output volt-
age. Do not remain in ramp up/down mode indefi nitely. The converter is
characterized and meets all its specifi cations only at the setpoint voltage
(plus or minus any trim voltage). During the ramp-up phase, the converter
is not considered fully in regulation. This may affect performance with
excessive high current loads at turn-on.
[7] The Sequence is a sensitive input into the feedback control loop of the
converter. Avoid noise and long leads on this input. Keep all wiring very
short. Use shielding if necessary.
[8] If one converter is slaving to another master converter, there will be a very
short phase lag between the two converters. This can usually be ignored.
[9] You may connect two or more Sequence inputs in parallel from two con-
verters. Be aware of the increasing pull-up bias current and reduced input
impedance.
LSN2-T/30-D12 Series
DOSA-SIP, 30A POL DC/DC Converters
MDC_LSN2-T/30-D12 Series.C01Δ Page 12 of 16
www.murata-ps.com/support
[10] Any external capacitance added to the converter’s output may affect ramp
up/down times and ramp tracking accuracy.
Pre-Biased Startup
Newer systems with multiple power voltages have an additional problem
besides startup sequencing. Some sections have power already partially
applied (possibly because of earlier power sequencing) or have leakage power
present so that the DC/DC converter must power up into an existing voltage.
This power may either be stored in an external bypass capacitor or supplied by
an active source.
This “pre-biased” condition can also occur with some types of program-
mable logic or because of blocking diode leakage or small currents passed
through forward biased ESD diodes. Conventional DC/DCs may fail to start up
correctly if there is output voltage already present. And some external circuits
are adversely affected when the low side MOSFET in a synchronous rectifi er
converter sinks current at start up.
The LSN2-T/30-D12 series includes a pre-bias startup mode to prevent
these initialization problems. Essentially, the converter acts as a simple buck
converter until the output reaches its set point voltage at which time it converts
to a synchronous rectifi er design. This feature is variously called “monotonic”
because the voltage does not decay (from low side MOSFET shorting) or
produce a negative transient once the input power is applied and the startup
sequence begins.
Don’t Use Pre-Biasing and Sequencing Together
Normally, you would use startup sequencing on multiple DC/DCs to solve the
Pre-Bias problem. By causing all power sources to ramp up together, no one
source can dominate and force the others to fail to start. For most applications,
do not use startup sequencing in a Pre-Bias application, especially with an
external active power source.
If you have active source pre-biasing, leave the Sequence input open so
that the output will step up quickly and safely. A symptom of this condition is
repeated failed starts. You can further verify this by removing the existing load
and testing it with a separate passive resistive load which does not exceed full
current. If the resistive load starts successfully, you may be trying to drive an
external pre-biased active source.
It may also be possible to use pre-bias and sequencing together if the Pre-
Bias source is in fact only a small external bypass capacitor slowly charged by
leakage currents. Test your application to be sure.
Output Adjustments
The LSN2-T/30-D12 series includes a special output voltage trimming feature
which is fully compatible with competitive units. The output voltage may be
varied using a single trim resistor from the Trim input to Power Common.
As with other trim adjustments, be sure to use a precision low-tempco resis-
tor (±100ppm/°C.) mounted close to the converter with short leads. Also be
aware that the output voltage accuracy is ±1.5% (typical) therefore you may
need to vary this resistance slightly to achieve your desired output setting.
Use short leads. Mount the leads close to the converter.
Resistor Trim Equation
Where VO is the desired output voltage.
R
TRIM (Ω) =
1200
− 100
V
O − 0.80
Figure 14. Trim Connections
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