78Q8392LA03-CHR/F

78Q8392L/A03
Low Power Ethernet
Coaxial Transceive
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Page: 1 of 14 © 2008 Teridian Semiconductor Corporation Rev 1.3
November 2008
DESCRIPTION
The 78Q8392L/A03 Ethernet Transceiver is a
replacement for the SSI/TDK/Teridian
78Q8392L/A02 coax line transmitter/receiver. Only a
single resistor value change is required for
upgrading an existing 78Q8392L/A02 design to the
78Q8392L/A03.
The device includes analog transmit and receive
buffers, a 10 MHz on-board oscillator, timing logic
for jabber and heartbeat functions, output drivers
and bandgap reference, in addition to a current
reference and collision detector.
This transceiver provides the interface between the
single-ended coaxial cable signals and the
Manchester-encoded differential logic signals.
Primary functional blocks include the receiver,
transmitter, collision detection and jabber timer. This
IC may be used in either internal or external MAU
environments.
The 78Q8392L/A03 is available in lead-free 16-pin
plastic and 28-pin PLCC packages.
FEATURES
Very low power consumption
Compliant with Ethernet II, IEEE 802.3
10Base5 and 10Base2
Integrates all transceiver functions except
signal and power isolation
Innovative design minimizes external
component count and power consumption
Jabber timer function integrated on chip
Externally selectable CED heartbeat allows
operation with IEEE 802.3 compatible
repeaters
Squelch circuitry at all inputs rejects noise
Power-on reset and test modes
Advanced BiCMOS process
CONNECT DIAGRAM
510 ±5%
x 4
CD+
CD–
RX+
RX–
TX+
TX-
COLLISION
SIGNAL
TO DTE
DATA TO
DTE
DATA FROM
DTE
VEE
VEE
GND
RR-
RR+
–9V
41
13
2
3
6
12
11
7
8
78
TXO
15
HBE
9
VEE
5
CDS
16
RXI
14
COAX
10
78Q8392L/A03
Low Power Ethernet
Coaxial Transceiver
Page: 2 of 14 © 2008 Teridian Semiconductor Corporation Rev 1.3
FUNCTIONAL DESCRIPTION
The 78Q8392L/A03 incorporates six basic functions
of the Ethernet Transceiver, including receiving,
transmitting, collision signaling, collision detection,
jabber timing, and the heartbeat function. Refer to
Figure 1 for a general system block diagram.
RECEIVER FUNCTIONS
The receiver senses signals through the RXI input,
which minimizes reflections on the transmission
media using a low capacitance, high resistance
input buffer amplifier. The CDS ground input
attaches directly to the input buffer from the coaxial
shield to eliminate ground loop noise.
In addition to the input buffer, the receiver data path
consists of an equalizer, data slicer, receiver
squelch circuitry, and an output line driver.
The equalizer improves the cable-induced jitter; the
data slicer restores equalized received signals to
fast transition signals with binary levels to drive the
receiver line driver; and the receiver line driver
drives the AUI cable through an isolation transformer
that connects to the AUI interface.
Noise on the transmission media is rejected by the
receiver squelch circuitry, which determines valid
data via three criteria: Average DC level, pulse
width and transition period. The DC voltage level is
detected and compared to a set level in the receiver
comparator circuit. The pulse width must be greater
than 20 ns to pass the narrow pulse filter; the
transition timer outputs a true level on the RX Data
Valid line provided the time between transitions is
less than about 200 ns. As long as a valid RXI signal
is detected, the output line driver remains enabled.
The transition timer disables the line driver when
there are no further transitions on the data medium,
and the RX+, RX- pins go to a zero differential
voltage state (Figure 3).
TRANSMITTER FUNCTIONS
The transmitter data path consists of a transmit input
buffer, pulse-shaping filter, transmit squelch
circuitry and transmit output line driver. The
self-biasing transmit input buffer receives data
through an isolation transformer and translates the
AUI differential analog signal to a square pulse
suitable for driving the pulse shaping filter.
The filter outputs a correctly shaped and band
limited signal to the transmit output driver, which
drives the transmission medium through a high
impedance current source. When the transmitter is
off, the capacitance of the transmit driver is isolated
from the transmission media by an external diode
with a low capacitance node. The shield of the
transmission media serves as the ground return for
the transmitter function.
A transmit squelch circuit, which consists of a pulse
threshold detector, a pulse width detector, and a
pulse duration timer, is used to suppress noise, as
well as crosstalk on the AUI cable. The squelch
circuitry disables the transmit driver if the signal at
TX+ or TX- is smaller than the pulse threshold.
Pulse noise is rejected by a pulse width detector that
passes only pulses with durations greater than 20
ns. The pulse duration timer disables the transmit
driver if no pulses are received for two-bit periods
following valid pulses. At the end of a transmission,
the pulse duration timer disables the transmitter and
triggers the blanking timer, used to block “dribble”
bits.
COLLISION DETECTION
A collision occurs when two or more transmitters
simultaneously transmit on the transmission media.
A collision is detected by comparing the average DC
level of the transmission media to a collision
threshold. The received signal at RXI is buffered and
sent through a low pass filter, then compared in the
collision threshold circuit. If the average DC level
exceeds a collision threshold, a 10 MHz signal is
output on the CD± pins.
COLLISION SIGNALING
When collision signaling is enabled (HBE pin is high
and the average DC level on RXI exceeds the
collision threshold V
CD
), a 10 MHz signal is sent from
the CD± pins through an isolation transformer to the
DTE. When the function is disabled, this output goes
to a zero differential state. The 10 MHz signal output
from the CD± pins indicates a collision on the
transmission media, a heartbeat function, or that the
transmitter is in jabber mode.
78Q8392L/A03
Low Power Ethernet
Coaxial Transceiver
Page: 3 of 14 © 2008 Teridian Semiconductor Corporation Rev 1.3
JABBER FUNCTION
When valid data on the TX± pins is detected, the
jabber timer is started. If there is valid data for more
than 20 ms, a latch is set which disables the
transmitter output and enables the 10 MHz output on
the CD± pins. The latch is reset within 0.5 seconds
after the valid data is removed from the transmitter
input (TX±). This action resets the jabber timer and
disables the 10 MHz signal on the CD± pins. The
TX± inputs must remain inactive during the 0.5
second reset period.
HEARTBEAT FUNCTION
The 10 MHz CD outputs are enabled for about 1 µs
at approximately 1.1 µs after the end of each
transmission. The heartbeat signal tells the DTE that
the circuit is functioning. This is implemented by
starting the heartbeat timer when the valid data
signal indicates the end of a transmission. This
function is disabled when HBE pin is tied to V
EE.
FIGURE 1: 78Q8392L/A03 General System Block Diagram
DATA MEDIA
RECEIVER
INPUT
BUFFER
RXI
CDS
EQUALIZER
SQUELCH
COMPARATOR
LP FILTER
SQUELSH
THRESHOLD
RX+
RX-
TXO
TRANSMIT
OUTPUT DRIVER
PULSE
SHAPING
FILTER
TX+
TX-
TRANSMIT INPUT
BUFFER
BANDGAP
REFERENCE
AND CURRENT
REFERENCE
10 MHz
OSC
RR+
RR-
CD+
CD-
SLICER
TRANSITION
PERIOD
TAMER
NARROW
PULSE
FILTER
RX DATA
VALID
ENABLE
SLICER
TX ON
CONTROL LOGIC
JABBER TIMER
BLANKING TIMER
HEART BEAT TIMER
TX DATA VALID
END TRANSMIT
TX± DISABLE
ENABLE
TX ± < -250 mV
TX ± > -250 mV
COMPARATOR
TX DISABLE
CD ± ON
COLLISION
THRESHOLD
COLLISION
COMPARATOR
BUFFERED TX
TRANSITION
PERIOD
TIMER
TRANSITION
END
TIMER
NARROW
PULSE
FILTER
SIGNAL
PRESET
DETECT

78Q8392LA03-CHR/F

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Ethernet ICs Ethernet Coaxial Transceiver
Lifecycle:
New from this manufacturer.
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