MPC9608 REVISION 4 MARCH 15, 2016 6 ©2016 Integrated Device Technology, Inc.
MPC9608 Data Sheet 1:10 LVCMOS ZERO DELAY CLOCK BUFFER
APPLICATIONS INFORMATION
Power Supply Filtering
The MPC9608 is a mixed analog/digital product. Its analog
circuitry is naturally susceptible to random noise, especially if
this noise is seen on the power supply pins. Random noise
on the V
CCA
(PLL) power supply impacts the device
characteristics, for instance I/O jitter. The MPC9608 provides
separate power supplies for the output buffers (V
CC
) and the
phase-locked loop (V
CCA
) of the device. The purpose of this
design technique is to isolate the high switching noise digital
outputs from the relatively sensitive internal analog
phase-locked loop. In a digital system environment where it
is more difficult to minimize noise on the power supplies a
second level of isolation may be required. The simple but
effective form of isolation is a power supply filter on the V
CCA
pin for the MPC9608. Figure 3 illustrates a typical power
supply filter scheme. The MPC9608 frequency and phase
stability is most susceptible to noise with spectral content in
the 100 kHz to 20 MHz range. Therefore the filter should be
designed to target this range. The key parameter that needs
to be met in the final filter design is the DC voltage drop
across the series filter resistor R
F
. From the data sheet the
I
CCA
current (the current sourced through the V
CCA
pin) is
typically 4 mA (8 mA maximum), assuming that a minimum of
3.125 V must be maintained on the V
CCA
pin. The resistor R
F
shown in Figure 3 must have a resistance of 9
– 10
(V
CC
= 3.3 V) to meet the voltage drop criteria.
The minimum values for R
F
and the filter capacitor C
F
are
defined by the required filter characteristics: the RC filter
should provide an attenuation greater than 40 dB for noise
whose spectral content is above 100 kHz. In the example RC
filter shown in Figure 3, the filter cut-off frequency is around
3-5 kHz and the noise attenuation at 100 kHz is better than
42 dB.
As the noise frequency crosses the series resonant point
of an individual capacitor, its overall impedance begins to
look inductive and thus increases with increasing frequency.
The parallel capacitor combination shown ensures that a low
impedance path to ground exists for frequencies well above
the bandwidth of the PLL. Although the MPC9608 has
several design features to minimize the susceptibility to
power supply noise (isolated power and grounds and fully
differential PLL), there still may be applications in which
overall performance is being degraded due to system power
supply noise. The power supply filter schemes discussed in
this section should be adequate to eliminate power supply
noise related problems in most designs.
Using the MPC9608 in Zero-Delay Applications
Nested clock trees are typical applications for the
MPC9608. Designs using the MPC9608, as LVCMOS PLL
fanout buffer with zero insertion delay, will show significantly
lower clock skew than clock distributions developed from
CMOS fanout buffers. The external feedback option of the
MPC9608 clock driver allows for its use as a zero delay
buffer. By using the QFB output as a feedback to the PLL the
propagation delay through the device is virtually eliminated.
The PLL aligns the feedback clock output edge with the clock
input reference edge resulting in a near zero delay through
the device. The maximum insertion delay of the device in
zero-delay applications is measured between the reference
clock input and any output. This effective delay consists of the
static phase offset, I/O jitter (phase or long-term jitter),
feedback path delay and the output-to-output skew error
relative to the feedback output.
Calculation of Part-to-Part Skew
The MPC9608 zero delay buffer supports applications
where critical clock signal timing can be maintained across
several devices. If the reference clock inputs of two or more
MPC9608 are connected together, the maximum overall
timing uncertainty from the common CCLK input to any
output is:
t
SK(PP)
= t
(
)
+ t
SK(O)
+ t
PD, LINE(FB)
+ t
JIT(
)
CF
This maximum timing uncertainty consists of 4 compo-
nents: static phase offset, output skew, feedback board trace
delay, and I/O (phase) jitter:
Figure 3. V
CCA
Power Supply Filter
V
CCA
V
CC
MPC9608
10 nF
R
F
= 9-10 for V
CC
= 3.3 V
C
F
33...100 nF
R
F
V
CC
C
F
= 1 F for V
CC
= 3.3 V
Figure 4. MPC9608 Maximum Device-to-Device Skew
t
PD,LINE(FB)
t
JIT()
+t
SK(O)
-t
()
+t
()
t
JIT()
+t
SK(O)
t
SK(PP)
Max. skew
CCLK
Common
QFB
Device 1
Any Q
Device 1
QFB
Device2
Any Q
Device 2
