13
LT1769
1769fa
APPLICATIONS INFORMATION
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Figure 7. Lower V
BOOST
SW
BOOST
SPIN
1769 F07
LT1769
V
X
I
VX
C2
D2
10µF
L1
+
thermal resistance of the package-board combination is
dominated by the characteristics of the board in the
immediate area of the package. This means both lateral
thermal resistance across the board and vertical thermal
resistance through the board to other copper layers. Each
layer acts as a thermal heat spreader that increases the
heat sinking effectiveness of extended areas of the board.
Total board area becomes an important factor when the
area of the board drops below about 20 square inches. The
graph in Figure 8 shows thermal resistance vs board area
for 2-layer and 4-layer boards with continuous copper
planes. Note that 4-layer boards have significantly lower
thermal resistance, but both types show a rapid increase
for reduced board areas. Figure 9 shows actual measured
lead temperatures for chargers operating at full current.
Battery voltage and input voltage will affect device power
dissipation, so the data sheet power calculations must be
used to extrapolate these readings to other situations.
Vias should be used to connect board layers together.
Planes under the charger area can be cut away from the
rest of the board and connected with vias to form both a
low thermal resistance system and to act as a ground plane
for reduced EMI.
Glue-on, chip-mounted heat sinks are effective only in
moderate power applications where the PC board copper
cannot be used, or where the board size is small. They offer
very little improvement in a properly laid out multilayer
board of reasonable size.
Higher Duty Cycle for the LT1769 Battery Charger
Maximum duty cycle for the LT1769 is typically 90%, but
this may be too low for some applications. For example, if
Example: V
IN
= 19V, V
BAT
= 12.6V, I
BAT
= 2A:
P 3.5mA 19 1.5mA 12.6
12.6
19
7.5mA 0.012 2000mA 0.35W
P
2 12.6
55 19
0.43W
P
2 0.16 12.6
19
10 19 2 200kHz
0.42 0.08 0.5W
BIAS
2
DRIVER
2
SW
2
9
=
()()
+
()
+
()
+
()( )
[]
=
=
()( )
+
()
=
=
()( )( )
+
()()( )
=+=
1
12 6
30
.
Total Power in the IC is: 0.35 + 0.43 + 0.5 = 1.3W
Temperature rise will be (1.3W)(35°C/W) = 46°C. This
assumes that the LT1769 is properly heat sunk by con-
necting the eleven fused ground pins to expanded traces
and that the PC board has a backside or internal plane for
heat spreading.
The P
DRIVER
term can be reduced by connecting the boost
diode D2 (see Figure 7) to a lower system voltage (lower
than V
BAT
) instead of V
BAT
.
Then P
DRIVER
=
()( )()
+
()
IVV
V
V
BAT BAT X
X
IN
1
30
55
For example, V
X
= 3.3V then:
P
AVV
V
V
W
DRIVER
=
()( )( )
+
()
=
2 126 33 1
33
30
55 19
009
..
.
.
The average I
VX
required is:
P
V
W
V
mA
DRIVER
X
==
009
33
28
.
.
The previous example shows the dramatic drop in driver
power dissipation when the boost diode (D2) is connected
to an external 3.3V source instead of the 12.6V battery.
P
DRIVER
drops from 0.43W to 0.09W resulting in an
approximately 12°C drop in junction temperature.
Fused-lead packages conduct most of their heat out the
leads. This makes it very important to provide as much PC
board copper around the leads as is practical. Total
14
LT1769
1769fa
APPLICATIONS INFORMATION
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Figure 11. Replacing the Input Diode
CHARGE CURRENT (A)
0
LEAD TEMPERATURE ON PINS 1, 2, 3 (°C)
40
50
2
1769 F09
30
20
0.5
1
1.5
70
60
NOTE: PEAK DIE TEMPERATURE
WILL BE ABOUT 15°C HIGHER AT
2A CHARGE CURRENT
V
IN
= 19V
V
BAT
= 12.3V
V
BOOST
= 5V
2-LAYER BOARD
ROOM TEMP = 24°C
5 IN
2
BOARD
25 IN
2
BOARD
BOARD AREA (IN
2
)
0
45
40
35
30
25
20
15
10
15 25
1769 F08
510
20 30 35
THERMAL RESISTANCE (°C/W)
MEASURED FROM AIR AMBIENT
TO DIE USING COPPER LANDS
AS SHOWN ON DATA SHEET
2-LAYER BOARD
4-LAYER BOARD
Figure 8. LT1769 Thermal Resistance
Figure 10. High Duty Cycle
V
IN
SW
BOOST
SPIN
SENSE BAT
V
CC
V
X
3V TO 6V
C
X
10µF
V
BAT
1769 F11
C2
0.47µF
D2
D1
R
X
50k
Q2
Q1
LT1769
HIGH DUTY CYCLE CONNECTION
Q1 = Si4435DY
Q2 = TP0610L
+
+
SW
BOOST
SPIN
SENSE BAT
V
BAT
C3
0.47µF
D2
LT1769
SW
BOOST
SPIN
SENSE BAT
V
X
3V TO 6V
C
X
10µF
V
BAT
1769 F10
C3
0.47µF
D2
LT1769
STANDARD CONNECTION HIGH DUTY CYCLE CONNECTION
+ +
an 18V ±3% adapter is used to charge ten NiMH cells, the
charger must put out approximaly 15V. A total of 1.6V is
lost in the input diode, switch resistance, inductor resis-
tance and parasitics, so the required duty cycle is
15/16.4 = 91.4%. The duty cycle can be extended to 93%
by restricting boost voltage to 5V instead of using V
BAT
as
is normally done. This lower boost voltage also reduces
power dissipation in the LT1769, so it is a win-win
decision. Connect an external source of 3V to 6V at V
X
node in Figure 10 with a 10µF C
X
bypass capacitor.
Lower Dropout Voltage
For even lower dropout and/or reducing heat on the board,
the input diode D3 can be replaced with a FET (see Figure
11). Connect a P-channel FET in place of the input diode
with its gate connected to the battery causing the FET to
turn off when the input voltage goes low. The problem is
that the gate must be pumped low so that the FET is fully
turned on even when the input is only a volt or two above
the battery voltage. Also there is a turn-off speed issue.
The FET should turn off instantly when the input is dead
shorted to avoid large current surges from the battery
back through the charger into the FET. Gate capacitance
slows turn-off, so a small P-channel (Q2) is added to
discharge the gate capacitance quickly in the event of an
input short. The Q2 body diode creates the necessary
pumping action to keep the gate of Q1 low during normal
operation. Note that Q1 and Q2 have a V
GS
spec limit of
20V. This restricts V
IN
to a maximum of 20V. For low
dropout operation with V
IN
> 20V consult factory.
Figure 9. LT1769 Lead Temperature
15
LT1769
1769fa
APPLICATIONS INFORMATION
WUU
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Optional Diode Connections
The typical application in Figure 1 shows a single diode
(D3) to isolate the V
CC
pin from the adaptor input and to
block reverse input voltage (both steady state and tran-
sient). This simple connection may be unacceptable in
situations where the system load must be powered from
the battery when the adapter input power is removed. As
shown in Figure 12, a parasitic diode exists from the SW
pin to the V
CC
pin in the LT1769. When the input power is
removed, this diode will become forward biased and will
provide a current path from the battery to the system load.
Because of diode power limitations, it is not recommended
to power the system load through the internal parasitic
diode. To safely power the system load from the battery,
an additional Schottky diode (D4) is needed. For minimum
losses, D4 could be replaced by a low R
DS(ON)
MOSFET
which is turned on when the adapter power is removed.
Layout Considerations
Switch rise and fall times are under 10ns for maximum
efficiency. To minimize radiation, the catch diode, SW pin
and input bypass capacitor leads should be kept as short
as possible. A ground plane should be used under the
switching circuitry to prevent interplane coupling and to
act as a thermal spreading path. All ground pins should be
connected to expanded traces for low thermal resistance.
The fast-switching high current ground path, including the
switch, catch diode and input capacitor, should be kept
very short. Catch diode and input capacitor should be
close to the chip and terminated to the same point. This
path contains nanosecond rise and fall times with several
amps of current. The other paths contain only DC and/or
200kHz tri-wave and are less critical. Figure 13 indicates
the high speed, high current switching path. Figure 14
shows critical path layout. Contact Linear Technology for
the LT1769 circuit PCB layout or Gerber file.
SW
L1
CLP
CLN
ADAPTER
IN
TO
SYSTEM
LOAD
R
S1
C
IN
R
S4
R7
500
C1
1µF
D3
LT1769
INTERNAL
PARASITIC
DIODE
V
CC
1769 F12a
D4
+
+
+
Figure 12. Modified Diode Connection Figure 13. High Speed Switching Path
1769 F13
V
BAT
L1
V
IN
HIGH
FREQUENCY
CIRCULATING
PATH
BAT
SWITCH NODE
C
IN
C
OUT
D1
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
C
IN
C
OUT
R
S1
D1
L1
GND
GND
1769 F14
TO
GND
TO
GND
NOTE: CONNECT ALL GND PINS TO EXPANDED PC LANDS FOR PROPER HEAT SINKING
GND
GND
GND
SW
BOOST
UV
GND
GND
OVP
CLP
CLN
COMP1
SENSE
GND
GND
GND
GND
V
CC1
V
CC2
V
CC3
GND
PROG
V
C
UV
OUT
COMP2
BAT
SPIN
GND
Figure 14. Critical Electrical and Thermal Path Layout

LT1769IGN#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Battery Management Const-C/Const-V 2A Bat Chr w/ In C Limin
Lifecycle:
New from this manufacturer.
Delivery:
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