NXP Semiconductors
TEA19051BT
USB-PD 2.0/USB-PD 3.0/QC 2.0/QC 3.0/QC 4 (+) controller for SMPS
TEA19051BT All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved.
Product data sheet Rev. 1 — 13 February 2018
7 / 36
8.1 Start-up and supply
The TEA19051BT is supplied via the VCC pin connected to the secondary DC voltage of
an AC-to-DC SMPS converter (see Figure 7). To control the primary side controller, this
VCC voltage is regulated via an integrated voltage/current control loop with external loop
compensation and an external optocoupler. This optocoupler is part of the gain loop of
the primary side SMPS controller.
At each start-up and after power-on reset, the optocoupler current is initially zero. So,
the AC-to-DC converter starts up with full output power, resulting in a rapid increase of
the VCC voltage. Due to the low V
CC(start)
level (≈3 V), the TEA19051BT ensures that it
is fully operating before the V
CC
reaches the default initial regulation level. The default
values of the initial regulation level are 5 V and 3 A and they are programmed in the non-
volatile memory (MTP).
At power-on reset, the safe default values, which are read from MTP, are set.
When the V
CC
voltage is below the UVLO level, the external NMOS load switch is off.
When the output is shorted while the load switch is closed, the UVLO is also triggered.
The load switch is then immediately opened and the system restarts after the safe restart
timer.
When the V
CC
exceeds the UVLO level, all circuits, the initial DAC value, and the
resistive divider ratio are initialized. The system regulates the output to 5 V with a limited
output current of 3 A. All these values can be set via the MTP.
To minimize the output voltage overshoot after start-up, an internal 20 mA current sink
is applied to VCC when the VCC voltage exceeds 1.05 × V
o(default)
. The sink current
remains active until the VCC voltage has dropped to below 1.05 × V
o(default)
again.
After the output voltage has stabilized, the load switch becomes conducting and the
system waits for an attach. Before the attach, only the essential circuits are working
which reduces the no-load power to its minimum.
When the voltage on one of the CC pins drops to below the V
IH(Rd)
level, an attach is
detected and all circuits are enabled.
If a protocol is detected, it is allowed to change the voltage and current.
5 V regulation
20 mA
discharge V
CC
reading EEPROM
initialization
1.05 x V
o(default)
UVLO
aaa-023848
Figure 3. Start-up sequence
The TEA19051BT operates on supply voltages up to 21 V. The voltage on the VCC pin is
used to detect an OVP and UVP. The OVP and UVP level are set as a percentage of the
requested output voltage level.
NXP Semiconductors
TEA19051BT
USB-PD 2.0/USB-PD 3.0/QC 2.0/QC 3.0/QC 4 (+) controller for SMPS
TEA19051BT All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved.
Product data sheet Rev. 1 — 13 February 2018
8 / 36
If the supply voltage drops to below the UVLO level, the system returns to the no-supply
state and opens the load switch. Analog circuits are reset below UVLO. The internal
digital circuits are reset below the band gap voltage reference level.
8.2 Voltage loop
The analog Constant Voltage (CV) loop regulates VCC such that the voltage on the
VSNS pin equals the internal reference voltage. An external resistor divider is connected
between VCC, the VSNS pin, and ground. The value of this divider must match the
value that is programmed in MTP exactly. It depends on the maximum voltage in the
application. The divider values are:
1/ 2.5; maximum PDO voltage ≤ 6 V
1/5.476; maximum PDO voltage ≤ 13 V
1/8.325; maximum PDO voltage ≤ 20 V
The CV loop is regulated by varying the current through an optocoupler diode similar
to a TL431 driven control loop commonly used in switch mode power supplies. The RC
combination between the OPTO and VSNS pin determines the dynamic behavior of
the integrating part of the control loop. The resistor in series with the optocoupler diode
determines the dynamic behavior of the proportional part of the control loop. To prevent
saturation of the control loop during switching, a diode is placed in parallel to this resistor.
See Section 13.3 for more information about the control loop.
When the voltage loop reference is set to a higher value using the USB-PD or the QC
protocol, the internal reference voltage is updated to the new setting within 20 μs. The
output voltage is regulated to the requested voltage with a speed determined by the
control loop. If there is a transition down, a predefined ramp down sequence is followed
to prevent a high undershoot. Depending on the step size, the ramp down either follows
a linear or a parabolic slope. For a transition up, no special measures are required to
prevent an overshoot. The reason is that the charging current of the loop capacitor lifts
the voltage on the VSNS pin when the V
CC
voltage in the application increases.
NXP Semiconductors
TEA19051BT
USB-PD 2.0/USB-PD 3.0/QC 2.0/QC 3.0/QC 4 (+) controller for SMPS
TEA19051BT All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved.
Product data sheet Rev. 1 — 13 February 2018
9 / 36
a. Circuit
aaa-021704
V
CC
discharge
loop saturated
V
opto
b. Curve
Figure 4. Linear transition down (no load)
A linear ramp-down (see Figure 4) can yield a perfect linear ramp of the output voltage
without any undershoot. However, depending on the loop bandwidth, the voltage loop
can end up in saturation. Saturation hampers a fast response to a load step immediately
following the end of the ramp (most protocols do not allow any load to be drawn during
a transition). Making the ramp down slower can prevent saturation of the loop. However,
a slower ramp down can contradict with the maximum discharge time most protocols
specify.
A parabolic discharge curve (see Figure 5; patent pending) initially causes the voltage
loop to saturate, due to the initial rapid ramp down. However, it allows the loop to recover
and to resume regulation toward the end of the curve. The total parabolic sequence time
must be chosen such that no undershoot under the final end value occurs.

TEA19051BAAT/1J

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
AC/DC Converters TEA19051BAAT/SO14//1/REEL 13 Q1 NDP
Lifecycle:
New from this manufacturer.
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