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N02L83W2AT25I

P1-P3P4-P6P7-P9P10-P10
N02L83W2A
©2008 SCILLC. All rights reserved. Publication Order Number:
July 2008 - Rev. 8 N02L83W2A/D
2Mb Ultra-Low Power Asynchronous CMOS SRAM
256K × 8 bit
Overview
The N02L83W2A is an integrated memory device
containing a 2 Mbit Static Random Access Memory
organized as 262,144 words by 8 bits. The device
is designed and fabricated using ON
Semiconductor’s advanced CMOS technology to
provide both high-speed performance and ultra-low
power. The device operates with two chip enable
(CE1
and CE2) controls and output enable (OE) to
allow for easy memory expansion. The
N02L83W2A is optimal for various applications
where low-power is critical such as battery backup
and hand-held devices. The device can operate
over a very wide temperature range of -40
o
C to
+85
o
C and is available in JEDEC standard
packages compatible with other standard 256Kb x
8 SRAMs
Features
• Single Wide Power Supply Range
2.3 to 3.6 Volts
• Very low standby current
2.0µA at 3.0V (Typical)
• Very low operating current
2.0mA at 3.0V and 1µs (Typical)
• Very low Page Mode operating current
0.8mA at 3.0V and 1µs (Typical)
• Simple memory control
Dual Chip Enables (CE1
and CE2)
Output Enable (OE
) for memory expansion
• Low voltage data retention
Vcc = 1.8V
• Very fast output enable access time
30ns OE
access time
• Automatic power down to standby mode
• TTL compatible three-state output driver
Pin Configuration
Product Family
Part Number Package Type
Operating
Temperature
Power
Supply (Vcc)
Speed
Standby
Current (I
SB
),
Typical
Operating
Current (Icc),
Typical
N02L83W2AT 32 - TSOP I
-40
o
C to +85
o
C
2.3V - 3.6V
55ns @ 2.7V
70ns @ 2.3V
2 µA2 mA @ 1MHz
N02L83W2AN 32 - STSOP I
N02L83W2AT2 32 - TSOP I Green
N02L83W2AN2 32 - STSOP I Green
N02L83W2A
STSOP-I, TSOP-I
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A11
A9
A8
A13
WE
CE2
A15
V
CC
A17
A16
A14
A12
A7
A6
A5
A4
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
V
SS
I/O2
I/O1
I/O0
A0
A1
A2
A3
Pin Descriptions
Pin Name Pin Function
A
0
-A
17
Address Inputs
WE
Write Enable Input
CE1
, CE2 Chip Enable Input
OE
Output Enable Input
I/O
0
-I/O
7
Data Inputs/Outputs
V
CC
Power
V
SS
Ground
Rev. 8 | Page 2 of 10 | www.onsemi.com
N02L83W2A
Functional Block Diagram
Functional Description
CE1 CE2 WE OE
I/O
0
- I/O
7
MODE POWER
H X X X High Z
Standby
1
1. When the device is in standby mode, control inputs (WE and OE), address inputs and data input/outputs are internally isolated
from any external influence and disabled from exerting any influence externally.
Standby
X L X X High Z
Standby
1
Standby
LHL
X
2
2. When WE is invoked, the OE input is internally disabled and has no effect on the circuit.
Data In
Write
2
Active
LHHL Data Out
Read
Active
L H H H High Z Active Active
Capacitance
1
1. These parameters are verified in device characterization and are not 100% tested
Item Symbol Test Condition Min Max Unit
Input Capacitance
C
IN
V
IN
= 0V, f = 1 MHz, T
A
= 25
o
C
8pF
I/O Capacitance
C
I/O
V
IN
= 0V, f = 1 MHz, T
A
= 25
o
C
8pF
Control
Logic
Page
Decode
Logic
Address
Inputs
A
4
- A
17
Input/
Output
Mux
and
Buffers
I/O
0
- I/O
7
Address
Word
Decode
Logic
Address
Address
Inputs
A
0
- A
3
16K Page
x 16 word
x 8 bit
RAM Array
Word Mux
CE1
CE2
WE
OE
Rev. 8 | Page 3 of 10 | www.onsemi.com
N02L83W2A
Absolute Maximum Ratings
1
1. Stresses greater than those listed above may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operating section of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Item Symbol Rating Unit
Voltage on any pin relative to V
SS
V
IN,OUT
–0.3 to V
CC
+0.3
V
Voltage on V
CC
Supply Relative to V
SS
V
CC
–0.3 to 4.5 V
Power Dissipation
P
D
500 mW
Storage Temperature
T
STG
–40 to 125
o
C
Operating Temperature
T
A
-40 to +85
o
C
Soldering Temperature and Time
T
SOLDER
260
o
C, 10sec
o
C
Operating Characteristics (Over Specified Temperature Range)
Item Symbol Test Conditions Min.
Typ
1
1. Typical values are measured at Vcc=Vcc Typ., T
A
=25°C and not 100% tested.
Max Unit
Supply Voltage
V
CC
2.3 3.0 3.6 V
Data Retention Voltage
V
DR
Chip Disabled
3
1.8 V
Input High Voltage
V
IH
1.8
V
CC
+0.3
V
Input Low Voltage
V
IL
–0.3 0.6 V
Output High Voltage
V
OH
I
OH
= 0.2mA V
CC
–0.2
V
Output Low Voltage
V
OL
I
OL
= -0.2mA
0.2 V
Input Leakage Current
I
LI
V
IN
= 0 to V
CC
0.5 µA
Output Leakage Current
I
LO
OE = V
IH
or Chip Disabled
0.5 µA
Read/Write Operating Supply Current
@ 1 µs Cycle Time
2
2. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add current required to drive
output capacitance expected in the actual system.
I
CC1
V
CC
=3.6 V, V
IN
=V
IH
or V
IL
Chip Enabled, I
OUT
= 0
2.0 4.0 mA
Read/Write Operating Supply Current
@ 70 ns Cycle Time
2
I
CC2
V
CC
=3.6 V, V
IN
=V
IH
or V
IL
Chip Enabled, I
OUT
= 0
12.0 16.0 mA
Page Mode Operating Supply Current
@ 70 ns Cycle Time
2
(Refer to Power
Savings with Page Mode Operation
diagram)
I
CC3
V
CC
=3.6 V, V
IN
=V
IH
or V
IL
Chip Enabled, I
OUT
= 0
4.0 mA
Read/Write Quiescent Operating Sup-
ply Current
3
3. This device assumes a standby mode if the chip is disabled (CE1 high or CE2 low). In order to achieve low standby current all
inputs must be within 0.2 volts of either VCC or VSS.
I
CC4
V
CC
=3.6 V, V
IN
=V
IH
or V
IL
Chip Enabled, I
OUT
= 0,
f = 0
3.0 mA
Maximum Standby Current
3
I
SB1
V
IN
= V
CC
or 0V
Chip Disabled
t
A
= 85
o
C, V
CC
= 3.6 V
2.0 20.0 µA
Maximum Data Retention Current
3
I
DR
V
CC
= 1.8V, V
IN
= V
CC
or 0
Chip Disabled, t
A
= 85
o
C
10.0 µA
P1-P3P4-P6P7-P9P10-P10

N02L83W2AT25I

Mfr. #:
Buy N02L83W2AT25I
Manufacturer:
ON Semiconductor
Description:
SRAM 2MB 3V LOW PWR SRAM
Lifecycle:
New from this manufacturer.
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