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ADG526AKPZ-REEL
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P20
ADG526A/ADG527A
Rev. C | Page 13 of 20
TIMING
Fig
ure
13
shows the timing sequence for lat
ching the switch
address and enable in
puts. The la
tches are level sensi
tive;
therefor
e, while
WR
is hel
d low
, t
he l
atches are t
ransp
arent and
the switches r
espond to the address and enab
le inputs. This
inp
ut data is latch
ed on the rising edge of
WR
.
3
V
0V
3V
0V
WR
EN
, A0,
A1,
A2, (
A3)
1.5V
2.0V
0.8V
t
W
t
S
t
H
01532-
003
Figure 13. Timing S
equence
Fig
ure
14
shows the reset pulse width, t
RS
, and reset turn-off
time,
t
OFF
(
RS
).
N
ote tha
t all digital in
put signal rise an
d fall times are m
easured
from 10% to 90% of 3 V
, t
R
= t
F
= 20 ns.
t
RS
t
OFF
(RS)
3
V
0V
V
O
0V
RS
0.8V
1.5V
SWI
TCH
O
UTPUT
01532-
004
Figure 14. Reset Pulse
ADG526A/ADG527A
Rev. C | Page 14 of 20
TEST CIRCUITS
SD
V
S
I
DS
V1
R
ON
=
V1
I
DS
0
1532-015
Figure 15. R
ON
A
V2
V1
I
S
(OFF
)
D
EN
GND
V
DD
V
SS
V
DD
V
SS
0.8V
01532-0
16
Figure 16. I
S
(Of
f
)
V
DD
V
SS
V
DD
V
SS
D
A
EN
GND
0.8V
V2
V
1
I
D
(OFF
)
01532-
017
Figure 17. I
D
(Of
f
)
V
DD
V
SS
V
DD
V
SS
V1
D
A
EN
GND
2.4V
V2
I
D
(ON)
01532-018
Figure 18. I
D
(On)
I
DIFF
= I
DA
(OFF
) – I
DB
(OFF
)
V
DD
V
SS
V
DD
V
SS
DA
A
GND
V
1
EN
V2
ADG527A
DB
A
0.8V
01532-019
Figure 19. I
DIFF
ADG526A/ADG527A
Rev. C | Page 15 of 20
3
V
0
V
ADDRESS
DRIVE
(V
IN
)
OUTPU
T
90%
90%
50%
t
TRANSI
TI
O
N
t
TRANSI
TI
O
N
*SIM
IL
AR CONNECT
I
ON F
OR ADG
527A.
50
Ω
V1
OU
TPU
T
ADG526A*
A2
A1
A0
2.4V
EN
GND
S1
S2 TO S15
S16
D
1M
Ω
35pF
A3
V2
WR
RS
V
IN
V
DD
V
SS
V
DD
V
SS
01532-0
20
Figure 20. Swit
ching Time
of Multiplex
er, t
TRANSITIO
N
*SIM
IL
AR CONNE
CTI
ON F
OR ADG
527A.
50
Ω
5V
OUTPU
T
ADG526A*
A2
A1
A0
2.4V
EN
GN
D
S1
S2 TO S15
S16
D
1k
Ω
35pF
A3
WR
RS
V
IN
V
DD
V
SS
V
DD
V
SS
3
V
0
V
ADDRESS
DRIVE
(V
IN
)
OUTPU
T
50%
t
OPE
N
0
1532-0
21
Figure 21. Break-Before-M
ake Delay, t
OPEN
*SIM
IL
AR CONNE
CTI
ON F
OR ADG
527A.
5V
OUTPU
T
ADG526A*
A2
A1
A0
2.4V
EN
GND
S1
S2 TO
S16
D
1k
Ω
35pF
A3
WR
50
Ω
V
IN
V
DD
V
SS
V
DD
V
SS
RS
3
V
0
V
ENABLE
DRIVE
(V
IN
)
OUTPU
T
10%
90%
50%
t
ON
(EN)
t
OFF
(EN)
01532-022
Figure 22. Enable De
lay, t
ON
(EN) t
OFF
(EN)
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P20
ADG526AKPZ-REEL
Mfr. #:
Buy ADG526AKPZ-REEL
Manufacturer:
Analog Devices Inc.
Description:
Multiplexer Switch ICs 16:1 CMOS Latched
Lifecycle:
New from this manufacturer.
Delivery:
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