MAX1265BCEI+ Datasheet MAX1265BEEI+, MAX1265ACEI+, MAX1265BCEI+ | P7-P9

MAX1265/MAX1267

265ksps, +3V, 6-/2-Channel, 12-Bit ADCs

with +2.5V Reference and Parallel Interface

_______________________________________________________________________________________ 7

Pin Description

D01010

INT

1111

1212

1313

CLK1414

D466

D377

D288

D199

D555

D644

D733

D822

Tri-State Digital I/O Line (D0)

INT goes low when the conversion is complete and output data is ready.

Active-Low Read Select. If CS is low, a falling edge on RD enables the read opera-

tion on the data bus.

Active-Low Write Select. When CS is low in the internal acquisition mode, a rising

edge on WR latches in configuration data and starts an acquisition plus a conver-

sion cycle. When CS is low in external acquisition mode, the first rising edge on WR

ends acquisition and starts a conversion.

Clock Input. In external clock mode, drive CLK with a TTL-/CMOS-compatible clock.

In internal clock mode, connect this pin to either V

or GND.

Tri-State Digital I/O Line (D4)

Tri-State Digital I/O Line (D3)

Tri-State Digital I/O Line (D2)

Tri-State Digital I/O Line (D1)

Tri-State Digital I/O Line (D5)

Tri-State Digital I/O Line (D6)

Tri-State Digital I/O Line (D7)

Tri-State Digital Output (D8)

Tri-State Digital Output (D9)

GND1923

REFADJ2024

CH2—19

CH11620

CH01721

COM1822

CH3—18

CH4—17

CH5—16

1515

Analog and Digital Ground

Bandgap Reference Output/Bandgap Reference Buffer Input. Bypass to GND with

a 0.01µF capacitor. When using an external reference, connect REFADJ to V

disable the internal bandgap reference.

Analog Input Channel 2

Analog Input Channel 1

Analog Input Channel 0

Ground Reference for Analog Inputs. Sets zero-code voltage in single-ended mode

and must be stable to ±0.5 LSB during conversion.

Analog Input Channel 3

Analog Input Channel 4

Analog Input Channel 5

Active-Low Chip Select. When CS is high, digital outputs (D11–D0) are high

impedance.

MAX1267MAX1265

NAME FUNCTION

MAX1265/MAX1267

265ksps, +3V, 6-/2-Channel, 12-Bit ADCs

with +2.5V Reference and Parallel Interface

8 _______________________________________________________________________________________

Pin Description (continued)

MAX1267

REF

2125

MAX1265

NAME

Bandgap Reference Buffer Output/External Reference Input. Add a 4.7µF capacitor

to GND when using the internal reference.

FUNCTION

26 22 V

Analog +2.7V to +3.6V Power Supply. Bypass with a 0.1µF capacitor to GND.

27 23 D11 Tri-State Digital Output (D11)

28 24 D10 Tri-State Digital Output (D10)

________________Detailed Description

Converter Operation

The MAX1265/MAX1267 ADCs use a successive-

approximation (SAR) conversion technique and an input

track/hold (T/H) stage to convert an analog input signal

to a 12-bit digital output. This output format provides an

easy interface to standard microprocessors (µPs). Figure

2 shows the simplified internal architecture of the

MAX1265/MAX1267.

Single-Ended and

Pseudo-Differential Operation

The sampling architecture of the ADC’s analog com-

parator is illustrated in the equivalent input circuit in

Figure 3. In single-ended mode, IN+ is internally

switched to channels CH0–CH5 for the MAX1265

(Figure 3a) and to CH0–CH1 for the MAX1267 (Figure

3b), while IN- is switched to COM (Table 2). In differen-

tial mode, IN+ and IN- are selected from analog input

pairs (Table 3) and are internally switched to either of

T/H

TRI-STATE, BIDIRECTIONAL

I/O INTERFACE

17kΩ

SUCCESSIVE-

APPROXIMATION

CHARGE REDISTRIBUTION

12-BIT DAC

CLOCK

ANALOG

INPUT

MULTIPLEXER

CONTROL LOGIC

AND

LATCHES

REF REFADJ

1.22V

REFERENCE

D0–D11

12-BIT DATA BUS

(CH5)

(CH4)

(CH3)

(CH2)

CH1

CH0

COM

CLK

INT

( ) ARE FOR MAX1265 ONLY.

GND

MAX1265

MAX1267

2.05

COMP

Figure 2. Simplified Functional Diagram of 6-/2-Channel MAX1265/MAX1267

MAX1265/MAX1267

265ksps, +3V, 6-/2-Channel, 12-Bit ADCs

with +2.5V Reference and Parallel Interface

_______________________________________________________________________________________ 9

BIT

PD1, PD0

D7, D6

PD1 and PD0 select the various clock and power-down modes.

Full power-down mode. Clock mode is unaffected.

D5 ACQMOD

ACQMOD = 0: Internal acquisition mode

ACQMOD = 1: External acquisition mode

NAME FUNCTIONAL DESCRIPTION

Standby power-down mode. Clock mode is unaffected.

Normal operation mode. External clock mode selected.

Normal operation mode. Internal clock mode selected.

SGL/DIF

SGL/DIF = 0: Pseudo-differential analog input mode

SGL/DIF = 1: Single-ended analog input mode

In single-ended mode, input signals are referred to COM. In differential mode, the voltage difference

between two channels is measured (Tables 2 and 4).

UNI/BIP

UNI/BIP = 0: Bipolar mode

UNI/BIP = 1: Unipolar mode

In unipolar mode, an analog input signal from 0V to V

REF

can be converted; in bipolar mode, the

signal can range from -V

REF

/2 to +V

REF

/2.

D2, D1, D0 A2, A1, A0

Address bits A2, A1, A0 select which of the 6/2 (MAX1265/MAX1267) channels are to be converted

(Tables 2 and 3).

Table 1. Control-Byte Functional Description

the analog inputs. This configuration is pseudo-differ-

ential in that only the signal at IN+ is sampled. The

return side (IN-) must remain stable within ±0.5 LSB

(±0.1 LSB for best performance) with respect to GND

during a conversion. To accomplish this, connect a

0.1µF capacitor from IN- (the selected input) to GND.

During the acquisition interval, the channel selected as

the positive input (IN+) charges capacitor C

HOLD

. At the

end of the acquisition interval, the T/H switch opens,

retaining charge on C

HOLD

as a sample of the signal

at IN+.

The conversion interval begins with the input multiplex-

er switching C

HOLD

from the positive input (IN+) to the

negative input (IN-). This unbalances node zero at the

comparator’s positive input. The capacitive digital-to-

analog converter (DAC) adjusts during the remainder

Figure 3a. MAX1265 Simplified Input Structure Figure 3b. MAX1267 Simplified Input Structure

CH0

CH1

CH2

CH3

CH4

CH5

COM

SWITCH

TRACK

T/H

SWITCH

800Ω

HOLD

12-BIT CAPACITIVE DAC

REF

ZERO

COMPARATOR

–

12pF

SINGLE-ENDED MODE: IN+ = CH0–CH5, IN- = COM

DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS

CH0/CH1, CH2/CH3, AND CH4/CH5

AT THE SAMPLING INSTANT,

THE MUX INPUT SWITCHES

FROM THE SELECTED IN+

CHANNEL TO THE SELECTED

IN- CHANNEL.

INPUT

MUX

CH0

CH1

COM

SWITCH

TRACK

T/H

SWITCH

800Ω

HOLD

12-BIT CAPACITIVE DAC

REF

ZERO

COMPARATOR

–

12pF

SINGLE-ENDED MODE: IN+ = CH0–CH1, IN- = COM

DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIR

CH0/CH1

AT THE SAMPLING INSTANT,

THE MUX INPUT SWITCHES

FROM THE SELECTED IN+

CHANNEL TO THE SELECTED

IN- CHANNEL.

INPUT

MUX

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P19

MAX1265BCEI+

Mfr. #:

Buy MAX1265BCEI+

Manufacturer:

Maxim Integrated

Description:

Analog to Digital Converters - ADC 12-Bit 6Ch 265ksps 3.6V Precision ADC

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

MAX1265BCEI+

MAX1265BCEI+

Products related to this Datasheet