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IDT 89HPES16T4AG2 Data Sheet
Power Management
– Utilizes advanced low-power design techniques to achieve low
typical power consumption
– Support PCI Express Power Management Interface specifica-
tion (PCI-PM 2.0)
– Unused SerDes are disabled.
– Supports Advanced Configuration and Power Interface Spec-
ification, Revision 2.0 (ACPI) supporting active link state
Testability and Debug Features
– Built in Pseudo-Random Bit Stream (PRBS) generator
– Numerous SerDes test modes
– Ability to read and write any internal register via the SMBus
– Ability to bypass link training and force any link into any mode
– Provides statistics and performance counters
Seven General Purpose Input/Output Pins
– Each pin may be individually configured as an input or output
– Each pin may be individually configured as an interrupt input
– Some pins have selectable alternate functions
Packaged in a 19mm x 19mm, 324-ball Flip Chip BGA with
1mm ball spacing
Product Description
Utilizing standard PCI Express interconnect, the PES16T4AG2
provides the most efficient fan-out solution for applications requiring high
throughput, low latency, and simple board layout with a minimum
number of board layers. It provides 16 GBps (128 Gbps) of aggregated,
full-duplex switching capacity through 16 integrated serial lanes, using
proven and robust IDT technology. Each lane provides 5 Gbps of band-
width in both directions and is fully compliant with PCI Express Base
Specification, Revision 2.0.
The PES16T4AG2 is based on a flexible and efficient layered archi-
tecture. The PCI Express layer consists of SerDes, Physical, Data Link
and Transaction layers in compliance with PCI Express Base specifica-
tion Revision 2.0. The PES16T4AG2 can operate either as a store and
forward or cut-through switch and is designed to switch memory and I/O
transactions. It supports eight Traffic Classes (TCs) and one Virtual
Channel (VC) with sophisticated resource management to enable effi-
cient switching and I/O connectivity for servers, storage, and embedded
processors with limited connectivity.
Figure 2 I/O Expansion Application
SMBus Interface
The PES16T4AG2 contains two SMBus interfaces. The slave inter-
face provides full access to the configuration registers in the
PES16T4AG2, allowing every configuration register in the device to be
read or written by an external agent. The master interface allows the
default configuration register values of the PES16T4AG2 to be over-
ridden following a reset with values programmed in an external serial
EEPROM. The master interface is also used by an external Hot-Plug I/O
expander.
Two pins make up each of the two SMBus interfaces. These pins
consist of an SMBus clock pin and an SMBus data pin. The Master
SMBus address is hardwired to 0x50, and the slave SMBus address is
hardwired to 0x77.
As shown in Figure 3, the master and slave SMBuses may be used
in a unified or split configuration. In the unified configuration, shown in
Figure 3(a), the master and slave SMBuses are tied together and the
PES16T4AG2 acts both as a SMBus master as well as a SMBus slave
on this bus. This requires that the SMBus master or processor that has
access to PES16T4AG2 registers supports SMBus arbitration. In some
systems, this SMBus master interface may be implemented using
general purpose I/O pins on a processor or micro controller, and may
not support SMBus arbitration. To support these systems, the
PES16T4AG2 may be configured to operate in a split configuration as
shown in Figure 3(b).
In the split configuration, the master and slave SMBuses operate as
two independent buses and thus multi-master arbitration is never
required. The PES16T4AG2 supports reading and writing of the serial
EEPROM on the master SMBus via the slave SMBus, allowing in
system programming of the serial EEPROM.
Memory
Memory
Memory
Processor
Memory
North
Bridge
PES16T4AG2
I/O
10GbE
I/O
10GbE
I/O
SATA
I/O
SATA
PCI Express
Slot
Processor
x8/x4
x4
x4
x4
