8
COMMERCIAL TEMPERATURE RANGE
IDT72V3652/72V3662/72V3672 3.3V CMOS SyncBiFIFO
TM
2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
FEBRUARY 4, 2009
IDT72V3652L10
(1)
IDT72V3652L15
IDT72V3662L10
(1)
IDT72V3662L15
IDT72V3672L10
(1)
IDT72V3672L15
Symbol Parameter Min. Max. Min. Max. Unit
f
S Clock Frequency, CLKA or CLKB — 100 — 66.7 MHz
tCLK Clock Cycle Time, CLKA or CLKB 10 — 15 — ns
t
CLKH Pulse Duration, CLKA or CLKB HIGH 4.5 — 6 — ns
t
CLKL Pulse Duration, CLKA and CLKB LOW 4.5 — 6 — ns
tDS Setup Time, A0-A35 before CLKA↑ and B0-B35 3 — 4 — ns
before CLKB↑
t
ENS1 Setup Time, CSA and W/RA, before 4 — 4.5 — ns
CLKA↑; CSB, and W/RB before CLKB↑
tENS2 Setup Time, ENA and MBA, before 3 — 4.5 — ns
CLKA↑; ENB, and MBB before CLKB↑
tRSTS Setup Time, RST1 or RST2 LOW before CLKA↑ 5—5—ns
or CLKB↑
(2)
tFSS Setup Time, FS0 and FS1 before RST1 and RST2 HIGH 7.5 — 7.5 — ns
tFWS Setup Time, FWFT before CLKA↑ 0—0—ns
tDH Hold Time, A0-A35 after CLKA↑ and B0-B35 after CLKB↑ 0.5 — 1 — ns
tENH Hold Time, CSA, W/RA, ENA, and MBA after CLKA↑; 0.5 — 1 — ns
CSB, W/RB, ENB, and MBB after CLKB↑
tRSTH Hold Time, RST1 or RST2 LOW after CLKA↑ or CLKB↑
(2)
4—4—ns
tFSH Hold Time, FS0 and FS1 after RST1 and RST2 HIGH 2 — 2 — ns
tSKEW1
(3)
Skew Time, between CLKA↑ and CLKB↑ for EFA/ORA, 7.5 — 7.5 — ns
EFB/ORB, FFA/IRA, and FFB/IRB
tSKEW2
(3,4)
Skew Time, between CLKA↑ and CLKB↑ for AEA,12—12—ns
AEB, AFA, and AFB
NOTES:
1. For 10ns speed grade:
Vcc = 3.3V ± 0.15V; TA = 0° to +70°.
2. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
3.
Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.
4. Design simulated, not tested.
TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE
(For 10ns speed grade only: Vcc = 3.3V ± 0.15V; TA = 0°C to +70°C; JEDEC JESD8-A compliant)