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LT1002ACN#PBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
7
LT1002
1002fb
Small Signal Transient Response
TYPICAL PERFORMANCE CHARACTERISTICS
U
W
FREQUENCY (Hz)
100
CHANNEL SEPARATION (dB)
160
150
140
130
120
110
100
90
80
1k 10k
1002 G19
100k 1M
V
S
= ±15V
T
A
= 25°C
R
S
=10Ω
R
S
=100Ω
R
S
=1k
Common Mode Rejection and
CMRR Match vs Frequency
Channel Separation vs Frequency
FREQUENCY (Hz)
COMMON MODE REJECTION (dB)
160
140
120
100
80
60
40
20
0
1002 G20
1
10
100 1k 10k 100k 1M
V
S
= ±15V
T
A
= 25°C
CMRR
MATCH ( CMRR)
<
Common Mode Limit
vs Temperature
TEMPERATURE (°C)
–50
V
+
–0.2
–0.4
–0.6
–0.8
–1.0
+1.0
+.8
+.6
+.4
+.2
V
–
25 75
1002 G21
–25 0
50 100 125
COMMON MODE LIMIT (VOLTS)
REFERRED TO POWER SUPPLY
V
–
= –1.2 to –4V
V
–
= –12 to –18V
V
+
= 12 to 18V
V
+
= 1.2 to 4V
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
2.0
1.5
1.0
0.5
±9 ±15
1002 G22
±3 ±6
±12
±18 ±21
–55°C
125°C
25°C
Supply Current vs. Supply Voltage
For Each Amplifier
Large Signal Transient Response
1002 G23
FREQUENCY (kHz)
1
OUTPUT VOLTAGE, PEAK-TO-PEAK (VOLTS)
28
24
20
16
12
8
4
0
10 100 1000
1002 G24
V
S
= ±15V
T
A
= +25°C
Maximum Undistorted
Output vs. Frequency
A
V
= +1, C
L
= 1000pF 1002 G27
Small Signal Transient Response
CAPACITIVE LOAD (PICOFARADS)
100
PERCENT OVERSHOOT
1002 G26
1000
10,000
100,000
100
80
60
40
20
0
V
S
= ±15V
T
A
= 25°C
V
IN
= 100mV
R
L
> 50k
Voltage Follower Overshoot
vs Capacitive Load
A
V
= +1, C
L
= 50pF 1002 G25
8
LT1002
1002fb
TYPICAL PERFORMANCE CHARACTERISTICS
U
W
LOAD RESISTANCE (Ω)
100 300
OUTPUT SWING (VOLTS)
16
12
8
4
0
1000 3k 10k
1002 G28
V
S
= ±15V
T
A
= 25°C
POSITIVE SWING
NEGATIVE SWING
TIME FROM OUTPUT SHORT (MINUTES)
0
SHORT CIRCUIT CURRENT (mA)
SINKING SOURCING
2
50
40
30
20
10
–10
–20
–30
–40
–50
1002 G29
134
–55°C
–55°C
25°C
25°C
125°C
125°C
V
S
= ±15V
Output Short Circuit Current
vs Time
Output Swing vs. Load Resistance
APPLICATIONS INFORMATION
WUU
U
The LT1002 dual amplifier may be inserted directly into
OP-10, OP207, OP227 sockets with or without removal of
external nulling potentiometers.
Offset Voltage Adjustment The input offset voltage of the
LT1002, and its drift with temperature, are permanently
trimmed at wafer testing to a low level. However, if further
adjustment of V
OS
is necessary, nulling with a 10k or 20k
potentiometer will not degrade drift with temperature.
Trimming to a value other than zero creates a drift of (V
OS
/
300)µV/°C, e.g. if V
OS
is adjusted to 300µV, the change in
drift will be 1µV/°C. The adjustment range with a 10k or
20k pot is approximately ±2.5mV. If less adjustment
range is needed, the sensitivity and resolution of the
nulling can be improved by using a smaller pot in conjunc-
tion with fixed resistors. The example has an approximate
null range of ±100µV.
In matching applications, both amplifiers can be trimmed
to zero, or the offset of one amplifier can be trimmed to
match the offset of the other. Offset adjustment, however,
slightly degrades the gain, common-mode and power-
supply rejection match between the two op amps. Fortu-
nately, the guaranteed offset voltage match of the LT1002
is very low, in most applications offset adjustment will be
unnecessary.
Improved Sensitivity Adjustment
Standard Adjustment
–
+
–15V
1/2
LT1002
15V
3
(10)
(11)
4
(9)
(8)
13 (6)
14 (7)
OUTPUT
INPUT
1002 TA03
12 (5)
2
10k
or
20k
1
–
+
–15V
1/2
LT1002
15V
3
(10)
(11)
4
(9)
(8)
13 (6)
14
OUTPUT
INPUT
1002 TA04
12 (5)
2
1k
7.5k
7.5k
1
(7)
9
LT1002
1002fb
APPLICATIONS INFORMATION
WUU
U
Test Circuit for Offset Voltage
and its Drift with Temperature
–
+
–15V
15V
50k*
100Ω*
50k*
3
(10)
(11)
4
14 (7)
13 (6)
V
O
1002 TA05
V
O
= 1000 V
OS
* RESISTORS MUST HAVE LOW
THERMOELECTRIC POTENTIAL.
12 (5)
1/2
LT1002
0.1Hz to 10Hz Noise Test Circuit
–
+
–
+
100k
2k
100k
4.3k
110k
SCOPE
× 1
R
IN
= 1MΩ
0.1µF
4.7µF
24.3k
10Ω
1002 TA06
0.1µF
22µF
VOLTAGE GAIN = 50,000
2.2µF
DEVICE
UNDER
TEST
A
1/2 LT1002
B
1/2 LT1002
PEAK TO PEAK NOISE MEASURED IN 10 SEC INTERVAL
This circuit is also used as burn-in configuration for the
LT1002, with supply voltages increased to ±20V.
Unless proper care is exercised, thermocouple effects,
caused by temperature gradients across dissimilar metals
at the contacts to the input terminals, can exceed the
inherent drift of the amplifier. Air currents should be
minimized, package leads should be short, the two input
leads should be as close together as possible and main-
tained at the same temperature.
Channel Separation
This parameter is defined as the ratio of the change in input
offset voltage of one amplifier to the change in output
voltage of the other amplifier causing the offset change.
At low frequencies the LT1002’s channel separation is an
almost unmeasurable 148dB. As frequency increases, pin
to pin capacitance of the package, between the output of
one amplifier and the inputs of the other, becomes domi-
nant. Since these pins are non-adjacent, the capacitance is
only 0.02pF. To maintain the LT1002’s excellent channel
separation at higher frequencies, the socket and PC board
capacitances should be minimized.
The device under test should be warmed up for three
minutes and shielded from air currents. Turn the device
180° to measure the noise of side B.
Power supplies
The LT1002 is specified over a wide range of power supply
voltages from ±3V to ±18V. Operation with lower supplies
is possible, down to ±1.2V (two Ni-Cad batteries). How-
ever, with ±1.2V supplies, the device is stable only in
closed loop gains of +2 or higher (or inverting gain of one
or higher).
The V+ supply terminals are completely independent and
may be powered by separate supplies if desired (this
approach, however, would sacrifice the advantages of the
power supply rejection ratio matching). The V– supply
terminals are both connected to the common substrate
and must be tied to the same voltage. Both V– pins should
be used.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

LT1002ACN#PBF

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Buy LT1002ACN#PBF
Manufacturer:
Analog Devices Inc.
Description:
Precision Amplifiers 2x, Matched Prec Op Amp
Lifecycle:
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