MT8806 Data Sheet
3
Zarlink Semiconductor Inc.
Functional Description
The MT8806 is an analog switch matrix with an array size of 8 x 4. The switch array is arranged such that there are
8 columns by 4 rows. The columns are referred to as the Y inputs/outputs and the rows are the X inputs/outputs.
The crosspoint analog switch array will interconnect any X I/O with any Y I/O when turned on and provide a high
degree of isolation when turned off. The control memory consists of a 32 bit write only RAM in which the bits are
selected by the address inputs (AY0-AY2, AX0 & AX1). Data is presented to the memory on the DATA input. Data is
asynchronously written into memory whenever both the CS (Chip Select) and the STROBE inputs are high and is
latched on the falling edge of STROBE. A logical “1” written into a memory cell turns the corresponding crosspoint
switch on and a logical “0” turns the crosspoint off. Only the crosspoint switches corresponding to the addressed
memory location are altered when data is written into memory. The remaining switches retain their previous states.
Any combination of X and Y inputs/outputs can be interconnected by establishing appropriate patterns in the control
memory. A logical “1” on the RESET input will asynchronously return all memory locations to logical “0” turning off
all crosspoint switches regardless of whether CS is high or low. Two voltage reference pins (V
SS
and V
EE
) are
provided for the MT8806 to enable switching of negative analog signals. The range for digital signals is from V
DD
to
V
SS
while the range for analog signals is from V
DD
to V
EE
. V
SS
and V
EE
pins can be tied together if a single voltage
reference is needed.
Address Decode
The five address inputs along with the STROBE and CS (Chip Select) inputs are logically ANDed to form an enable
signal for the resettable transparent latches. The DATA input is buffered and is used as the input to all latches. To
write to a location, RESET must be low and CS must go high while the address and data are set up. Then the
STROBE input is set high and then low causing the data to be latched. The data can be changed while STROBE is
high, however, the corresponding switch will turn on and off in accordance with the DATA input. DATA must be
stable on the falling edge of STROBE in order for correct data to be written to the latch.
13 15 V
EE
Negative Power Supply
14-16 16,17, 20 AY0-AY2 Y0 -Y2 Address Lines (Inputs)
17 21 STROBE STROBE (Input): enables function selected by address and data. Address must
be stable before STROBE goes high and DATA must be stable on the falling
edge of the STROBE. Active High.
18 22 RESET Master RESET (Input): this is used to turn off all switches regardless of the
condition of CS. Active High.
19-23 23-27 Y7-Y3 Y7-Y3 Analog (Inputs/Outputs): these are connected to the Y7-Y3 columns of
the switch array.
24 28 VDD Positive Power Supply
4, 5,
18, 19
NC No Connect
Pin Description
Pin #
Name Description
PDIP PLCC
