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BU2506FV-E2

P1-P3P4-P6P7-P9P10-P11
BU2506FV,BU2505FV
Technical Note
4/10
www.rohm.com
2011.04 - Rev.B
© 2011ROHM Co., Ltd. All rights reserved.
●Cascade Connection
A data output terminal for cascade connection (DO) is available for reducing the number of parts when it is increased.
The DO terminal can be connected to a data input terminal (DI) of the next IC.
However, DO transition is synchronized with rising edge of clock signal, DO signal should be delayed, to keep a limit of data hold
time.
For example RC passive filter can be used.
Also in some cases, an operation frequency of logic signal have to be decreased to ensure a margin of data setup time.
Therefore, it is better to control LD port of each LSI separately, if extra CPU ports are available.
In this case, more ports to control LD signals are needed, but a consideration described above doesn’t have do be done.
BU2505FV
BU2506FV
(#2)
BU 2505FV
BU
2506FV
(
#1)
LD
CLK
DI
LD
CLK
DI
LD 1
LD 2
DI
CLK
BU2505FV
BU2506FV
DO
LD
CLK
DI
(#2)
BU2505FV
BU2506FV
DO
LD
CLK
DI
(#1)
CPU
LD
CLK
DI
BU2506FV,BU2505FV
Technical Note
5/10
www.rohm.com
2011.04 - Rev.B
© 2011ROHM Co., Ltd. All rights reserved.
BU2505FV BU2506FV
●Terminal Descriptions
No.
Terminal
Name
Analog /
Digital
I/O Description
Equivalent
Circuit
1 VSS Analog -
DA converter lower standard voltage (VrefL) input terminal
6
2 AO3 Analog O
10bit D/A output(CH3)
4
3 AO4 Analog O
10bit D/A output(CH4)
4
4 AO5 Analog O
10bit D/A output(CH5)
4
5 Reverse Digital I
The reverse LSB and MSB of data designation 10bit in 14bit.
2
6 Reset Digital I
All ch analog output L fixed
2
7 AO6 Analog O
10bit D/A output(CH6)
4
8 AO7 Analog O
10bit D/A output(CH7)
4
9 AO8 Analog O
10bit D/A output(CH8)
4
10 VDD Analog -
DA converter upper standard voltage (VrefH) input terminal
5
11 VCC - -
Power source terminal
-
12 AO9(TEST1) Analog O
10bit D/A output(CH9) (BU2506FV : test terminal)
4
13 AO10(TEST2) Analog O
10bit D/A output(CH10) (BU2506FV : test terminal)
4
14 DO Digital O
This outputs bit data of LSB of 14bit shift register.
3
15 LD Digital I
LD terminal. When High level is input, the value of 14bit shift
register is loaded to decoder and D/A output register.
1
16 CLK Digital I
Shift clock input terminal. At rise of shift clock, the signal from
DI terminal is input to 14bit shift register.
1
17 DI Digital I
Serial data input terminal. Serial data whose data length is 14bit
(address 4bit + data 10bit) is input.
1
18 AO1 Analog O
10bit D/A output(CH1)
4
19 AO2 Analog O
10bit D/A output(CH2)
4
20 GND - -
GND terminal
-
*In the case of BU2506FV, be sure to leave the TEST1 and TEST2 terminals open
D/A
14bit
Shift register
L
1
10bit R-2R
DA converter
10bit Latch
Ch2
・・・
・・・
Ch3
10bit Latch
Buffer
operation
amplifier
10bit R-2R
DA converter
Address
decoder
D0
1
2
3
4
5
6
D9
D10 11 12 D13
10
D/A
L
7
L
D/A
6
L
D/A
5
L
D/A
4
D/A
10987654321
VDDAO8AO7AO6ResetReverseAO5AO4AO3VSS
(VrefH)(VrefL)
11121314151617181920
VCCAO9AO10DOLDCLKDIAO1AO2GND
7
8
D/A
L
9
8
L
D/A
L
14bit
Shift register
1
10bit R-2R
DA converter
10bit Latch
Ch2
・・・
・・・
Ch3
10bit Latch
Buffer
operation
amplifier
10bit R-2R
DA converter
Address
decoder
D0
1
2
3
4
5
6
D9
D10 11 12 D13
D/A
L
7
L
D/A
6
L
D/A
5
L
D/A
4
D/A
10987654321
VDDAO8AO7AO6ResetReverseAO5AO4AO3VSS
(VrefH)(VrefL)
11121314151617181920
VCCTEST1TEST2DOLDCLKDIAO1AO2GND
7
8
8
L
D/A
L
BU2506FV,BU2505FV
Technical Note
6/10
www.rohm.com
2011.04 - Rev.B
© 2011ROHM Co., Ltd. All rights reserved.
D 0D 1D 2D3 D13D12D 11
DI
CLK
LD
DACOUT
D 4
A
DDRESS
LSB
A
DDRESS
MSB
DATA
MSB
DATA
LSB
●Command Transmission
1) Reverse = open (or VCC short-circuit) setting
(1) Data format
(2) Data timing diagram
D3 D2 D1 D0 Address Selection
0 0 0 0 Inconsequential
0 0 0 1 AO1 selection
0 0 1 0 AO2 selection
0 0 1 1 AO3 selection
0 1 0 0 AO4 selection
0 1 0 1 AO5 selection
0 1 1 0 AO6 selection
0 1 1 1 AO7 selection
1 0 0 0 AO8 selection
1 0 0 1 AO9 selection
*1
1 0 1 0 AO10 selection
*1
1 0 1 1 Inconsequential
1 1 0 0 Inconsequential
1 1 0 1 Inconsequential
1 1 1 0 Inconsequential
1 1 1 1 Inconsequential
D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D/A output (VrefH=VDD, VrefL=VSS)
0 0 0 0 0 0 0 0 0 0 VrefL
0 0 0 0 0 0 0 0 0 1 (VrefH-VrefL)/1024×1+VrefL
0 0 0 0 0 0 0 0 1 0 (VrefH-VrefL)/1024×2+VrefL
0 0 0 0 0 0 0 0 1 1 (VrefH-VrefL)/1024×3+VrefL
: : : : : : : : : : :
1 1 1 1 1 1 1 1 1 0 (VrefH-VrefL)/1024×1022+VrefL
1 1 1 1 1 1 1 1 1 1 (VrefH-VrefL)/1024×1023+VrefL
2) Reverse = L setting
(1) Data format
(2) Data timing diagram
D3 D2 D1 D0 Address selection
0 0 0 0 Inconsequential
0 0 0 1 AO1 selection
0 0 1 0 AO2 selection
0 0 1 1 AO3 selection
0 1 0 0 AO4 selection
0 1 0 1 AO5 selection
0 1 1 0 AO6 selection
0 1 1 1 AO7 selection
1 0 0 0 AO8 selection
1 0 0 1 AO9 selection
*1
1 0 1 0 AO10 selection
*1
1 0 1 1 Inconsequential
1 1 0 0 Inconsequential
1 1 0 1 Inconsequential
1 1 1 0 Inconsequential
1 1 1 1 Inconsequential
D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D/A output (VrefH=VDD, VrefL=VSS)
0 0 0 0 0 0 0 0 0 0 VrefL
1 0 0 0 0 0 0 0 0 0 (VrefH-VrefL)/1024×1+VrefL
0 1 0 0 0 0 0 0 0 0 (VrefH-VrefL)/1024×2+VrefL
1 1 0 0 0 0 0 0 0 0 (VrefH-VrefL)/1024×3+VrefL
: : : : : : : : : : :
0 1 1 1 1 1 1 1 1 1 (VrefH-VrefL)/1024×1022+VrefL
1 1 1 1 1 1 1 1 1 1 (VrefH-VrefL)/1024×1023+VrefL
*1 In the BU2506FV, this channel is for testing, therefore, do not designate.
For D/A converter output setting
For address selection
For D/A converter output setting
For address selection
D 0D1D 2D3 D4D5D 6
DI
CLK
LD
DACOUT
D13
DATA
MSB
DATA
LSB
A
DDRESS
LSB
A
DDRESS
MSB
P1-P3P4-P6P7-P9P10-P11

BU2506FV-E2

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Description:
Digital to Analog Converters - DAC 10 BIT D/A CNVTR 20-Pin
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