Evaluation Board User Guide
UG-019
One Technology Way • P. O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Te l: 781.329.4700 • Fax: 781.461.3113 • www.analog.com
Universal Evaluation Board for Dual, High Speed Op Amps
Offered in 8-Lead SOT-23 Packages
PLEASE SEE THE LAST PAGE FOR AN IMPORTANT
WARNING AND LEGAL TERMS AND CONDITIONS.
Rev. 0 | Page 1 of 8
FEATURES
Enables quick breadboarding/prototyping
User-defined circuit configuration
Edge-mounted SMA connector provisions
Easy connection to test equipment and other circuits
RoHS Compliant
GENERAL DESCRIPTION
The Analog Devices, Inc., high speed universal evaluation
board (EB-O8RJ-2Z) is designed to help customers quickly
prototype new dual op amp circuits and reduce design time.
The evaluation board can be used with almost any Analog
Devices dual op amp in various configurations and applications.
Figure 1 shows the component side of the bare evaluation board,
and Figure 2 shows the circuit side of the bare evaluation board.
The evaluation board is a 2-layer PCB that accepts SMA connectors
on the input and output for efficient connection to test equipment.
The ground plane, component placement, and supply bypassing
are laid out to minimize parasitic inductances and capacitances.
The evaluation board components are primarily SMT 0805 case
size, with the exception of the electrolytic bypass capacitors
(C1, C2), which are 3528 case size.
There are two options for supply bypassing. The first option is
connecting additional shunt capacitors (C3, C4) in parallel with
the electrolytic capacitors (C1, C2) from each supply to ground.
This technique of power supply bypassing provides wideband
rejection of unwanted noise on the supply lines. It is implemented
by placing a 0 Ω resistor in the C5 position and shunt capacitors
in the C1, C2, C3, and C4 positions.
The second approach to supply bypassing connects one capacitor
between the supply rails. This method uses fewer components and
can improve the power supply rejection ratio (PSRR) at higher
frequencies. It is implemented by inserting a 0 Ω resistor in the C3
position, inserting the bypass capacitor in the C4 position, and
omitting C5. Optimal bypassing is circuit dependent and therefore
must be evaluated by the designer.
Figure 3 shows the evaluation board schematic. Figure 4 and
Figure 6 show the evaluation board assembly drawings. The
PCB layout pattern for the component side is shown in Figure 5,
and the PCB layout pattern for the circuit side is shown in
Figure 7.
EVALUATION BOARD COMPONENT AND CIRCUIT SIDE DIAGRAMS
08146-001
NOTES
1. THE EVALUATION BOARD SILKSCREEN PART
NUMBER LABELING ON YOUR BOARD MAY
BE DIFFERENT FROM WHAT IS SHOWN HERE.
Figure 1. EB-O8RJ-2Z Component Side of Evaluation Board
08146-002
NOTES
1. THE EVALUATION BOARD SILKSCREEN PART
NUMBER LABELING ON YOUR BOARD MAY
BE DIFFERENT FROM WHAT IS SHOWN HERE.
Figure 2. EB-O8RJ-2Z Circuit Side of Evaluation Board
