NCP349
http://onsemi.com
10
Undervoltage Lockout (UVLO)
To ensure proper operation under any conditions, the
device has a built−in undervoltage lockout (UVLO) circuit.
During V
in
positive going slope, the output remains
disconnected from input until V
in
voltage is below UVLO,
plus hysteresis, nominal. The FLAG output is tied to low as
long as V
in
does not reach UVLO threshold. This circuit has
a built−in hysteresis to provide noise immunity to transient
condition. Additional UVLO thresholds ranging from
UVLO can be manufactured. Contact your
ON Semiconductor representative for availability.
Overvoltage Lockout (OVLO)
To protect connected systems on V
out
pin from
overvoltage, the device has a built−in overvoltage lockout
(OVLO) circuit. During overvoltage condition, the output
remains disabled as long as the input voltage exceeds
typical OVLO. Additional OVLO thresholds ranging from
OVLO can be manufactured. Contact your ON
Semiconductor representative for availability.
FLAG output is tied to low until V
in
is higher than OVLO.
This circuit has a built−in hysteresis to provide noise
immunity to transient conditions.
FLAG Output
The NCP349 provides a FLAG output, which alerts
external systems that a fault has occurred.
This pin is tied to low as soon the OVLO threshold is
exceeded or when the V
in
level is below the UVLO
threshold. When V
in
level recovers normal condition,
FLAG is held high, keeping in mind that an additional t
start
delay has been added between available output and FLAG
= high. The pin is an open drain output, thus a pull up
resistor (typically 1 MW, minimum 10 kW) must be added
to V
bat
. Minimum V
bat
supply must be 2.5 V. The FLAG
level will always reflects V
in
status, even if the device is
turned off (EN = 1).
EN Input
To enable normal operation, the EN pin shall be forced
to low or connected to ground. A high level on the pin,
disconnects OUT pin from IN pin. EN does not overdrive
an OVLO or UVLO fault.
Internal NMOS FET
The NCP349 includes an internal Low R
DS(on)
NMOS
FET to protect the systems, connected on OUT pin, from
positive overvoltage. Regarding electrical characteristics,
the R
DS(on)
, during normal operation, will create low losses
on V
out
pin.
As example: R
load
= 8.0 W, V
in
= 5.0 V
Typical R
DS(on)
= 65 mW, I
out
= 618 mA
V
out
= 8 x 0.618 = 4.95 V
NMOS losses = R
DS(on)
x Iout
2
= 0.065 x 0.618
2
= 25 mW
ESD Tests
The NCP349 input pin fully supports the IEC61000−4−2.
1.0 mF (minimum) must be connected between V
in
and
GND, close to the device.
That means, in Air condition, V
in
has a ±15 kV ESD
protected input. In Contact condition, V
in
has ±8.0 kV ESD
protected input.
Please refer to Figure 19 to see the IEC 61000−4−2
electrostatic discharge waveform.
Figure 19. Electrostatic Discharge Waveform
PCB Recommendations
The NCP349 integrates a 2 A rated NMOSFET, and the
PCB rules must be respected to properly evacuate the heat
out of the silicon. The pin 7 (exposed pad) is internally
connected to the internal NMOS Drain (Input). This
exposed pad must be used to increase heat transfer and must
be connected to Pin 1. Of course, in any case, this pad
shall be not connected to any other potential.
Figure 20.
60
80
100
120
140
160
180
200
0 100 200 300 400 500 600 700
Copper heat spreader area (mm^2)
Theta JA (C/W)
0.25
0.5
0.75
1
1.25
1.5
1.75
Max Power
W
Theta JA curve with PCB cu thk 1.0 oz
Theta JA curve with PCB cu thk 2.0 oz
Power curve with PCB cu thk 2.0 oz
Power curve with PCB cu thk 1.0 oz
