LTC4266A/LTC4266C
23
4266acfd
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APPLICATIONS INFORMATION
may also short from gate to drain, causing the LTC4266A/
LTC4266C GATE pin to rise to an abnormally high voltage.
The LTC4266A/LTC4266C OUT, SENSE and GATE pins
are designed to tolerate up to 80V faults without damage.
If the LTC4266A/LTC4266C sees any of these conditions
for more than 180μs, it disables all port functionality,
reduces the gate drive pull-down current for the port and
reports a FET Bad fault. This is typically a permanent fault,
but the host can attempt to recover by resetting the port,
or by resetting the entire chip if a port reset fails to clear
the fault. If the MOSFET is in fact bad, the fault will quickly
return, and the port will disable itself again. The remaining
ports of the LTC4266A/LTC4266C are unaffected.
An open or missing MOSFET will not trigger a FET Bad fault,
but will cause a t
START
fault if the LTC4266A/LTC4266C
attempts to turn on the port.
Voltage and Current Readback
The LTC4266A/LTC4266C measures the output voltage
and current at each port with an internal A/D converter.
Port data is only valid when the port power is on. The
converter has two modes:
• Slow mode: 14 samples per second, 14.5 bits resolution
• Fast mode: 440 samples per second, 9.5 bits resolution
In fast mode, the least significant 5 bits of the lower byte
are zeroes so that bit scaling is the same in both modes.
Disconnect
The LTC4266A/LTC4266C monitors the port to make
sure that the PD continues to draw the minimum speci-
fied current. A disconnect timer counts up whenever port
current is below 7.5mA (typ), indicating that the PD has
been disconnected. If the t
DIS
timer expires, the port will
be turned off and the disconnect bit in the fault event reg-
ister will be set. If the current returns before the t
DIS
timer
runs out, the timer resets and will start counting from the
beginning if the undercurrent condition returns. As long
as the PD exceeds the minimum current level more often
than t
DIS
, it will stay powered.
Although not recommended, the DC disconnect feature can
be disabled by clearing the corresponding DC Disconnect
Enable bits. Note that this defeats the protection mecha-
nisms built into the IEEE spec, since a powered port will
stay powered after the PD is removed. If the still-powered
port is subsequently connected to a non-PoE data device,
the device may be damaged.
The LTC4266A/LTC4266C does not include AC disconnect
circuitry, but includes AC Disconnect Enable bits to main-
tain compatibility with the LTC4259A. If the AC Disconnect
Enable bits are set, DC disconnect will be used.
Shutdown Pins
The LTC4266A/LTC4266C includes a hardware SHDN pin
for each port. When a SHDN pin is pulled to DGND, the
corresponding port will be shut off immediately. The port
remains shut down until re-enabled via I
2
C or a device
reset in AUTO pin mode.
Masked Shutdown
The LTC4266
A/LTC4266C provides a low latency port
shedding feature to quickly reduce the system load when
required. By allowing a pre-determined set of ports to
be turned off, the current on an overloaded main power
supply can be reduced rapidly while keeping high priority
devices powered. Each port can be configured to high or
low priority; all low-priority ports will shut down within
6.5μs after the MSD pin is pulled low. If multiple ports in
a LTC4266A/LTC4266C device are shut down via MSD,
they are staggered by at least 0.55μs to help reduce volt-
age transients on the main supply. If a port is turned off
via MSD, the corresponding Detection and Classification
Enable bits are cleared, so the port will remain off until
the host explicitly re-enables detection.
SERIAL DIGITAL INTERFACE
Overview
The LTC4266A/LTC4266C communicates with the host us-
ing a standard SMBus/I
2
C 2-wire interface. The LTC4266A/
LTC4266C is a slave-only device, and communicates with
the host master using the standard SMBus protocols.
Interrupts are signaled to the host via the INT pin. The
Timing Diagrams (Figures 5 through 9) show typical