N25S830HA
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Table 8. CONTROL SIGNAL DESCRIPTIONS
Signal Name I/O Description
CS Chip Select I A low level selects the device and a high level puts the device in standby mode. If CS is brought
high during a program cycle, the cycle will complete and then the device will enter standby mode.
When CS is high, SO is in high−Z. CS must be driven low after power−up prior to any sequence
being started.
SCK Serial Clock I Synchronizes all activities between the memory and controller. All incoming addresses, data and
instructions are latched on the rising edge of SCK. Data out is updated on SO after the falling edge
of SCK.
SI Serial Data In I Receives instructions, addresses and data on the rising edge of SCK.
SO Serial Data Out O Data is transferred out after the falling edge of SCK.
HOLD Hold I A high level is required for normal operation. Once the device is selected and a serial sequence is
started, this input may be taken low to pause serial communication without resetting the serial se-
quence. The pin must be brought low while SCK is low for immediate use. If SCK is not low, the
Hold function will not be invoked until the next SCK high to low transition. The device must remain
selected during this sequence. SO is high−Z during the Hold time and SI and SCK are inputs are
ignored. To resume operations, HOLD
must be pulled high while the SCK pin is low.
Lowering the HOLD
input at any time will take to SO output to High−Z.
Functional Operation
Basic Operation
The 256 Kb serial SRAM is designed to interface directly
with a standard Serial Peripheral Interface (SPI) common on
many standard micro−controllers. It may also interface with
other non−SPI ports by programming discrete I/O lines to
operate the device.
The serial SRAM contains an 8−bit instruction register
and is accessed via the SI pin. The CS
pin must be low and
the HOLD
pin must be high for the entire operation. Data is
sampled on the first rising edge of SCK after CS
goes low.
If the clock line is shared, the user can assert the HOLD
input
and place the device into a Hold mode. After releasing the
HOLD
pin, the operation will resume from the point where
it was held.
The following table contains the possible instructions and
formats. All instructions, addresses and data are transferred
MSB first and LSB last.
Table 9. INSTRUCTION SET
Instruction Instruction Format Description
READ 0000 0011 Read data from memory starting at selected address
WRITE 0000 0010 Write data to memory starting at selected address
RDSR 0000 0101 Read status register
WRSR 0000 0001 Write status register
READ Operations
The serial SRAM READ is selected by enabling CS low.
First, the 8−bit READ instruction is transmitted to the device
followed by the 16−bit address with the MSB being a don’t
care. After the READ instruction and addresses are sent, the
data stored at that address in memory is shifted out on the SO
pin after the output valid time from the clock edge.
If operating in page mode, after the initial word of data is
shifted out, the data stored at the next memory location on
the page can be read sequentially by continuing to provide
clock pulses. The internal address pointer is automatically
incremented to the next higher address on the page after each
word of data is read out. This can be continued for the entire
page length of 32 words long. At the end of the page, the
addresses pointer will be wrapped to the 0 word address
within the page and the operation can be continuously
looped over the 32 words of the same page.
If operating in burst mode, after the initial word of data is
shifted out, the data stored at the next memory location can
be read sequentially by continuing to provide clock pulses.
The internal address pointer is automatically incremented to
the next higher address after each word of data is read out.
This can be continued for the entire array and when the
highest address is reached (7FFFh), the address counter
wraps to the address 0000h. This allows the burst read cycle
to be continued indefinitely.
All READ operations are terminated by pulling CS
high.
