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IS62WV10248DBLL-55TLI-TR

P1-P3P4-P6P7-P9P10-P12P13-P15
10 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
05/11/09
IS62WV10248DALL/BLL, IS65WV10248DALL/BLL
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,2)
(OverOperatingRange)
45ns
55 ns
70 ns
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
tW C WriteCycleTime 45 — 55 — 70 — ns
tS C S 1/tS C S 2 CS1/CS2toWriteEnd 35 — 45 — 60 — ns
tA W AddressSetupTimetoWriteEnd 35 — 45 — 60 — ns
th A AddressHoldfromWriteEnd 0 — 0 — 0 — ns
tS A AddressSetupTime 0 — 0 — 0 — ns
tP W e
(4)
WEPulseWidth 35 — 40 — 50 — ns
tS d DataSetuptoWriteEnd 20 — 25 — 30 — ns
th d DataHoldfromWriteEnd 0 — 0 — 0 — ns
th z W e
(3)
WELOWtoHigh-ZOutput — 20 — 20 — 30 ns
tL z W e
(3)
WEHIGHtoLow-ZOutput 5 — 5 — 5 — ns
Notes:
1. Testconditionsassumesignaltransitiontimesof5nsorless,timingreferencelevelsof0.9V/1.5V,inputpulselevelsof0.4to
V
d d -0.2V/0.4VtoVd d -0.3VandoutputloadingspeciedinFigure1.
2.
Theinternalwritetimeisdenedbytheoverlapof CS1 LOW,CS2HIGH,andWELOW.AllsignalsmustbeinvalidstatestoinitiateaWrite,butanyonecan
go inactive to
terminatetheWrite.TheDataInputSetupandHoldtimingarereferencedtotherisingorfallingedgeofthesignalthatterminatesthewrite.
3. TestedwiththeloadinFigure2.Transitionismeasured±500mVfromsteady-statevoltage.Not100%tested.
4.t
P W e
> th z W e + tS d when OEisLOW.
AC WAVEFORMS
WRITE CYCLE NO. 1 (CS1/CS2 Controlled, OE=HIGHorLOW)
DATA-IN VALID
DATA UNDEFINED
t
WC
t
SCS1
t
SCS2
t
AW
t
HA
t
PWE
t
HZWE
HIGH-Z
t
LZWE
t
SA
t
SD
t
HD
ADDRESS
CS1
CS2
WE
DOUT
DIN
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 11
Rev. A
05/11/09
IS62WV10248DALL/BLL, IS65WV10248DALL/BLL
WRITE CYCLE NO. 2 (WEControlled:OEisHIGHDuringWriteCycle)
WRITE CYCLE NO. 3 (WEControlled:OEisLOWDuringWriteCycle)
DATA-IN VALID
DATA UNDEFINED
t
WC
t
SCS1
t
SCS2
t
AW
t
HA
t
PWE
t
HZWE
HIGH-Z
t
LZWE
t
SA
t
SD
t
HD
ADDRESS
OE
CS1
CS2
WE
DOUT
DIN
DATA-IN VALID
DATA UNDEFINED
t
WC
tSCS1
tSCS2
t
AW
tHA
tPWE
tHZWE
HIGH-Z
tLZWE
tSA
tSD tHD
ADDRESS
OE
CS1
CS2
WE
DOUT
DIN
12 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
05/11/09
IS62WV10248DALL/BLL, IS65WV10248DALL/BLL
DATA RETENTION WAVEFORM (CS1 Controlled)
V
DD
CS1 V
DD
- 0.2V
t
SDR
t
RDR
V
DR
CS1
GND
Data Retention Mode
DATA RETENTION SWITCHING CHARACTERISTICS (1.65V - 3.6V)
Symbol Parameter Test Condition Min. Typ.* Max. Unit
Vd r Vd d forDataRetention SeeDataRetentionWaveform 1.4 3.6 V
Id r DataRetentionCurrent Vd d =1.4V,CS1 ≥ Vd d –0.2V Com. — 4 20 µA
Ind. — 40
Auto. — 95
tS d r DataRetentionSetupTime SeeDataRetentionWaveform 0 — ns
tr d r RecoveryTime SeeDataRetentionWaveform tr C — ns
DATA RETENTION WAVEFORM (CS2 Controlled)
V
DD
CS2 0.2V
t
SDR
t
RDR
V
DR
CE2
GND
Data Retention Mode
* Typical Values are measured at VDD = 3V, TA = 25
o
C and not 100% tested.
P1-P3P4-P6P7-P9P10-P12P13-P15

IS62WV10248DBLL-55TLI-TR

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Buy IS62WV10248DBLL-55TLI-TR
Manufacturer:
ISSI
Description:
SRAM 8M (1Mx8) 55ns Async SRAM
Lifecycle:
New from this manufacturer.
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