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MAX5083ATE+T

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
MAX5082/MAX5083
1.5A, 40V, MAXPower Step-Down
DC-DC Converters
10 ______________________________________________________________________________________
pump is omitted and the input voltage range is from
7.5V to 40V. In this situation, the boost diode and the
boost capacitor are still required (see the MAX5083
Typical Operating Circuit).
Gate Drive Supply (DVREG)
DVREG is the supply input for the internal high-side
MOSFET driver. The power for DVREG is derived from
the output of the internal regulator (REG). Connect
DVREG to REG externally. We recommend the use of
an RC (1Ω and 0.47µF) filter from REG to DVREG to fil-
ter the noise generated by the switching of the charge
pump. In the MAX5082, the high-side drive supply is
generated using the internal charge pump along with
the bootstrap diode and capacitor. In the MAX5083, the
high-side MOSFET driver supply is generated using
only the bootstrap diode and capacitor.
Error Amplifier
The output of the internal error amplifier (COMP) is avail-
able for frequency compensation (see the Compensation
Design section). The inverting input is FB, the noninvert-
ing input SS, and the output COMP. The error amplifier
has an 80dB open-loop gain and a 1.8MHz GBW prod-
uct. See the Typical Operating Character-istics for the
Gain and Phase vs. Frequency graph.
Oscillator/Synchronization Input (SYNC)
With SYNC tied to SGND, the MAX5082/MAX5083 use
their internal oscillator and switch at a fixed frequency
of 250kHz. For external synchronization, drive SYNC
with an external clock from 150kHz to 350kHz. When
driven with an external clock, the device synchronizes
to the rising edge of SYNC.
PWM Comparator/Voltage Feed-Forward
An internal 250kHz ramp generator is compared
against the output of the error amplifier to generate the
PWM signal. The maximum amplitude of the ramp
(V
RAMP
) automatically adjusts to compensate for input
voltage and oscillator frequency changes. This causes
the V
IN
/V
RAMP
to be a constant 10V/V across the input
voltage range of 4.5V to 40V (MAX5082) or 7.5V to 40V
(MAX5083) and the SYNC frequency range of 150kHz
to 350kHz.
Output Short-Circuit Protection
(Hiccup Mode)
The MAX5082/MAX5083 protects against an output short
circuit by utilizing hiccup-mode protection. In hiccup
mode, a series of sequential cycle-by-cycle current-limit
events will cause the part to shut down and restart with
a soft-start sequence. This allows the device to operate
with a continuous output short circuit.
During normal operation, the current is monitored at the
drain of the internal power MOSFET. When the current
limit is exceeded, the internal power MOSFET turns off
until the next on-cycle and a counter increments. If the
counter counts four consecutive current-limit events,
the device discharges the soft-start capacitor and
shuts down for 512 clock periods before restarting with
a soft-start sequence. Each time the power MOSFET
turns on and the device does not exceed the current
limit, the counter is reset.
Thermal-Overload Protection
The MAX5082/MAX5083 feature an integrated thermal-
overload protection. Thermal-overload protection limits
the total power dissipation in the device and protects it
in the event of an extended thermal fault condition.
When the die temperature exceeds +160°C, an internal
thermal sensor shuts down the part, turning off the
power MOSFET and allowing the IC to cool. After the
temperature falls by 20°C, the part will restart with a
soft-start sequence.
Applications Information
Setting the Undervoltage Lockout
When the voltage at ON/OFF rises above 1.23V, the
MAX5082/MAX5083 turns on. Connect a resistive
divider from IN to ON/OFF to SGND to set the UVLO
threshold (see Figure 5). First select the ON/OFF to the
SGND resistor (R2) then calculate the resistor from IN
to ON/OFF (R1) using the following equation:
where V
IN
is the input voltage at which the converter
turns on, V
ON/OFF
= 1.23V and R2 is chosen to be less
than 600kΩ.
If the external UVLO divider is not used, connect
ON/OFF to IN directly. In this case, an internal under-
voltage lockout feature monitors the supply voltage at
IN and allows operation to start when IN rises above
4.1V (MAX5082) and 7.1V (MAX5083).
Setting the Output Voltage
Connect a resistive divider from OUT to FB to SGND to
set the output voltage (see Figure 5). First calculate the
resistor from OUT to FB using the guidelines in the
Compensation Design section. Once R3 is known, cal-
culate R4 using the following equation:
RR
V
V
12 1=×
⎡
⎣
⎢
⎢
⎤
⎦
⎥
⎥
−
IN
ON/OFF
MAX5082/MAX5083
1.5A, 40V, MAXPower Step-Down
DC-DC Converters
______________________________________________________________________________________ 11
where V
FB
= 1.23V.
Inductor Selection
Three key inductor parameters must be specified for
operation with the MAX5082/MAX5083: inductance
value (L), peak inductor current (I
PEAK
), and inductor
saturation current (I
SAT
). The minimum required induc-
tance is a function of operating frequency, input-to-out-
put voltage differential, and the peak-to-peak inductor
current (∆I
P-P
). Higher ∆I
P-P
allows for a lower inductor
value while a lower ∆I
P-P
requires a higher inductor
value. A lower inductor value minimizes size and cost
and improves large-signal and transient response, but
reduces efficiency due to higher peak currents and
higher peak-to-peak output voltage ripple for the same
output capacitor. On the other hand, higher inductance
increases efficiency by reducing the ripple current.
Resistive losses due to extra wire turns can exceed the
benefit gained from lower ripple current levels especial-
ly when the inductance is increased without also allow-
ing for larger inductor dimensions. A good compromise
is to choose ∆I
P-P
equal to 40% of the full load current.
Calculate the inductor using the following equation:
V
IN
and V
OUT
are typical values so that efficiency is opti-
mum for typical conditions. The switching frequency
(f
SW
) is fixed at 250kHz or can vary between 150kHz and
350kHz when synchronized to an external clock (see the
Oscillator/Synchronization Input (SYNC) section). The
peak-to-peak inductor current, which reflects the peak-to-
peak output ripple, is worst at the maximum input voltage.
See the Output Capacitor Selection section to verify that
the worst-case output ripple is acceptable. The inductor
saturating current (I
SAT
) is also important to avoid run-
away current during continuous output short circuit.
Select an inductor with an I
SAT
specification higher than
the maximum peak current limit of 3.5A.
Input Capacitor Selection
The discontinuous input current of the buck converter
causes large input ripple currents and therefore the
input capacitor must be carefully chosen to keep the
input voltage ripple within design requirements. The
input voltage ripple is comprised of ∆V
Q
(caused by the
capacitor discharge) and ∆V
ESR
(caused by the ESR of
the input capacitor). The total voltage ripple is the sum
of ∆V
Q
and ∆V
ESR
. Calculate the input capacitance and
ESR required for a specified ripple using the following
equations:
where
I
OUT_MAX
is the maximum output current, D is the duty
cycle, and f
SW
is the switching frequency.
The MAX5082/MAX5083 includes internal and external
UVLO hysteresis and soft-start to avoid possible unin-
tentional chattering during turn-on. However, use a bulk
capacitor if the input source impedance is high. Use
enough input capacitance at lower input voltages to
avoid possible undershoot below the undervoltage
lockout threshold during transient loading.
Output Capacitor Selection
The allowable output voltage ripple and the maximum
deviation of the output voltage during load steps deter-
mine the output capacitance and its ESR. The output
ripple is mainly composed of ∆V
Q
(caused by the
capacitor discharge) and ∆V
ESR
(caused by the volt-
age drop across the equivalent series resistance of the
output capacitor). The equations for calculating the
peak-to-peak output voltage ripple are:
Normally, a good approximation of the output voltage
ripple is ∆V
RIPPLE
≈∆V
ESR
+ ∆V
Q
. If using ceramic
capacitors, assume the contribution to the output volt-
age ripple from ESR and the capacitor discharge to be
∆
∆
∆∆
V
I
1
VI
Q
P-P
OUT SW
ESR P
-
P
=
××
=×
6C f
ESR
()
∆I
VV V
VL
D
V
V
P
-
P
IN OUT OUT
IN SW
OUT
IN
=
×
××
=
−
f
and
ESR
V
I
IDD
f
=
+
⎛
⎝
⎜
⎞
⎠
⎟
=
×
×
−
∆
∆
∆
ESR
OUT_MAX
P
-
P
IN
OUT_MAX
QSW
I
C
1
V
2
()
()
L
f
=
××
−VVV
VI
OUT IN OUT
IN SW P
-
P
∆
R
R
V
V
4
3
1
=
⎡
⎣
⎢
⎤
⎦
⎥
−
OUT
FB
MAX5082/MAX5083
1.5A, 40V, MAXPower Step-Down
DC-DC Converters
12 ______________________________________________________________________________________
equal to 20% and 80%, respectively. ∆I
P-P
is the peak-to-
peak inductor current (see the Input Capacitors Selection
section) and f
SW
is the converter’s switching frequency.
The allowable deviation of the output voltage during
fast load transients also determines the output capaci-
tance, its ESR, and its equivalent series inductance
(ESL). The output capacitor supplies the load current
during a load step until the controller responds with a
greater duty cycle. The response time (t
RESPONSE
)
depends on the closed-loop bandwidth of the converter
(see the Compensation Design section). The resistive
drop across the output capacitor’s ESR, the drop
across the capacitor’s ESL (∆V
ESL
), and the capacitor
discharge causes a voltage droop during the load-
step. Use a combination of low-ESR tantalum/aluminum
electrolyte and ceramic capacitors for better transient
load and voltage ripple performance. Nonleaded
capacitors and capacitors in parallel help reduce the
ESL. Keep the maximum output voltage deviation
below the tolerable limits of the electronics being pow-
ered. Use the following equations to calculate the
required ESR, ESL, and capacitance value during a
load step:
where I
STEP
is the load step, t
STEP
is the rise time of the
load step, and t
RESPONSE
is the response time of the
controller.
Compensation Design
The MAX5082/MAX5083 use a voltage-mode control
scheme that regulates the output voltage by comparing
the error amplifier output (COMP) with an internal ramp
to produce the required duty cycle. The output lowpass
LC filter creates a double pole at the resonant frequen-
cy, which has a gain drop of -40dB/decade. The error
amplifier must compensate for this gain drop and phase
shift to achieve a stable closed-loop system.
The basic regulator loop consists of a power modulator,
an output feedback divider, and a voltage-error amplifi-
er. The power modulator has a DC gain set by
V
IN
/V
RAMP
, with a double pole and a single zero set by
the output inductance (L), the output capacitance
(C
OUT
) (C5 in the Typical Application Circuit) and its
equivalent series resistance (ESR). The power modula-
tor incorporates a voltage feed-forward feature, which
automatically adjusts for variations in the input voltage
resulting in a DC gain of 10. The following equations
define the power modulator:
The switching frequency is internally set at 250kHz or
can vary from 150kHz to 350kHz when driven with an
external SYNC signal. The crossover frequency (f
C
),
which is the frequency when the closed-loop gain is
equal to unity, should be set at 15kHz or below therefore:
f
C
≤ 15kHz
The error amplifier must provide a gain and phase
bump to compensate for the rapid gain and phase loss
from the LC double pole. This is accomplished by utiliz-
ing a type 3 compensator that introduces two zeroes
and 3 poles into the control loop. The error amplifier
has a low-frequency pole (f
P1
) near the origin.
The two zeros are at:
and the higher frequency poles are at:
Compensation When f
C
< f
ZESR
Figure 3 shows the error amplifier feedback as well as
its gain response for circuits that use low-ESR output
capacitors (ceramic). In this case f
ZESR
occurs after f
C
.
f
Z1
is set to 0.8 x f
LC(MOD)
and f
Z2
is set to f
LC
to com-
pensate for the gain and phase loss due to the double
pole. Choose the inductor (L) and output capacitor
(C
OUT
) as described in the Inductor and Output
Capacitor Selection section.
f
RC
and f
R
CC
CC
PP23
1
266
1
25
78
78
=
××
=
××
×
+
⎛
⎝
⎜
⎞
⎠
⎟
π
π
f
1
f
1
Z1 Z2
=
××
=
×+×257 2 636ππRC
and
RR C()
G
V
V
f
LC
f
C ESR
MOD DC
IN
RAMP
LC
OUT
ZESR
OUT
()
==
=
×
=
××
10
1
2
1
2
π
π
E
V
C
V
E
V
ESR
STEP
OUT
STEP RESPONSE
Q
ESL STEP
STEP
SR
I
It
SL
t
I
=
=
=
×
×
∆
∆
∆
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

MAX5083ATE+T

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Buy MAX5083ATE+T
Manufacturer:
Maxim Integrated
Description:
Switching Voltage Regulators 1A 40V MAXPower Step-Down
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